target.nr

vxworks bsp for pc pentium3 开发环境为tornado2.2 for pentium。

    /@ ATA controller two resources @/
    {
        /@  PCCARD_RESOURCE @/
        { 
        ATA2_VCC,           /@ 3-5 volts Vcc @/
        ATA2_VPP,           /@ 5-12 volts Vpp @/
            {
            ATA2_IO_START0, /@ start I/O address 0 @/
            ATA2_IO_START1  /@ start I/O address 1 @/
            },  

            {
            ATA2_IO_STOP0,  /@ end I/0 address 0 @/
            ATA2_IO_STOP1   /@ end I/0 address 1 @/
            }, 
        ATA2_EXTRA_WAITS,   /@ extra wait states 0-2 @/
        ATA2_MEM_START,     /@ start host mem address @/
        ATA2_MEM_STOP,      /@ stop host mem address @/
        ATA2_MEM_WAITS,     /@ mem extra wait states 0-2 @/
        ATA2_MEM_OFFSET,    /@ mem offset of card address @/
        ATA2_MEM_LENGTH     /@ length of memory @/
        },
    ATA2_CTRL_TYPE,         /@ IDE_LOCAL or ATA_PCMCIA @/
    ATA2_NUM_DRIVES,        /@ number of drives on controller @/ 
    INT_NUM_ATA2,           /@ interrupt number of controller @/
    ATA2_INT_LVL,           /@ interrupt level of controller @/
    ATA2_CONFIG,            /@ device configuration settings @/
    ATA2_SEM_TIMEOUT,       /@ semaphore timeout for controller @/
    ATA2_WDG_TIMEOUT,       /@ watchdog timeout for controller @/
    ATA2_SOCKET_TWIN,       /@ socket number for twin card @/
    ATA2_POWER_DOWN         /@ power down mode for this controller @/
    }
    };
...
.CE

where the table initialization elements are constants defined in the BSP
config.h file.

The size of the <ataResources> table, and the number of ATA controllers
supported by ataDrv, are specified by the ATA_MAX_CTRLS constant which
is defined in the $WIND_BASE/target/h/drv/hdisk/ataDrv.h file.  By
default, ATA_MAX_CTRLS is set to value 2 under the assumption that
ataDrv will support at most 2 controllers.  When the <ataResources> table
is modified to specify more than two controllers, as in the example
above, the ATA_MAX_CTRLS constant should be redefined and the
$WIND_BASE/target/src/drv/hdisk/ataDrv.c file should be rebuilt prior
to building a vxWorks image with the new configuration.

.IP "aic7880Lib"
A device driver for the AHA-2940 PCI SCSI Adapter card is provided.  This
card houses the AIC-7880 Adaptec SCSI Host Adapter.  Configure a system to
use the AIC-7880 driver by defining the INCLUDE_AIC_7880 configuration
constant in the BSP config.h file.

Note that the AIC-7880 PCI SCSI Adapter card driver for x86 requires SCSI-2.
The configuration constants, INCLUDE_SCSI and INCLUDE_SCSI2, must be defined
in config.h in order to configure SCSI-2 support into a system.  Also note
that, as the AIC-7880 is a PCI card, the INCLUDE_PCI configuration
constant will be defined in the config.h file when INCLUDE_AIC_7880 is
defined.

The default Interrupt Request (IRQ) Channel number used by x86 BSPs for
the SCSI interrupt may be assigned by a system BIOS.  The IRQ number
assigned by a BIOS should not conflict with other interrupts in the
system (Eg. Ethernet).  If a VxWorks system is configured to use "forced"
PCI configuration by setting the PCI_CFG_TYPE configuration to the value
PCI_CFG_FORCE, then the IRQ number will default to the value specified by
AIC7880_INT_LVL in the BSP pc.h file.  The AIC7880_INT_LVL is set to 0x0a
by default.  Modify this value if necessary to prevent conflicts with
other devices installed on the system built to use forced PCI configuration.
It is recommended that one use the CMOS setup menu to set the IRQ number
for a SCSI Host Adapter when appropriate to the particular hardware and
system being configured.

If SCSI configuration fails, it can be the result of improper SCSI bus 
termination.  Check your hardware setup.

For information regarding installation and configuration of the AHA-2940,
see the "Adaptec 7800 Family Manager Set User's Guide".

.IP "i8253Timer"
This library contains a board-independent interface for manipulating the
timer functions on Intel 8253 and compatible timer chip devices.  This
library provides system clock and the auxiliary clock functions.

Configuration macros in the BSP can be used to modify how the system clock
and auxiliary clock facilities are implemented via i8253-compatible devices.
However, it is strongly recommended that users consult the documentation
for the target hardware platform prior to using certain configuration
macros related to the i8253Timer driver configuration.  In particular,
users should know how the outputs of the timer channels are connected on
the target hardware platform.

As an example of why it is important to consider how an 8253-compatible
device is integrated into the system, consider how such devices were often
implemented in legacy consumer desktop applications.  The 8253-compatible
chips usually contain three timers.  Typically, all three timers are driven
by a 14.31818 MHz crystal input from the system board, divided by 12, to
yield a 1.19318 MHz input clock to the timers.  The outputs from each
timer channel were, and are, often connected as follows in desktop
systems:

.bS
                       8253
                 +---------------+
                 |    Timer 2    |
 from bit 0      |         output+------> to speaker circuitry
 of port 61h ----+->gate         |
                 |               |
 1.19318 MHz ----+->clk 2        |
                 |               |
                 +---------------+
                 |    Timer 1    |
 +5 V            |         output+------> DRAM refresh
 (logic 1)--+----+->gate         |
            |    |               |
 1.19318 MHz ----+->clk 1        |
            |    |               |
            |    +---------------+
            |    |    Timer 0    |
            |    |         output+------> to IRQ0 (timer interrupt)
            +----+->gate         |
                 |               |
 1.19318 MHz ----+->clk 0        |
                 |               |
                 +---------------+
.bE

As indicated in the diagram, the output of timer channel 2 is connected to
nothing other than the speaker.  The output of timer 2 is not connected to
the 8259 PIC or other type of interrupt controller.

The output from timer channel 1 is dedicated to providing DRAM refresh.
As a result, this timer should not be manipulated once it is programmed
appropriately for the system DRAM.

Because the output from timer channel 0 in the example above is connected
to an interrupt controller and is not used as a time base for a system
critical function (i.e., DRAM refresh), timer 0 is a good candidate for use
as a programmable system or auxiliary clock device.

The example above is but one possible way 8253-compatible timer devices
might be integrated into a target system.  Some system boards may connect
all timer channel outputs to an interrupt controller.  Not every system
will connect timer channel outputs to DRAM refresh or to a speaker.
Again, users are encouraged to consult the target hardware documentation
in order to understand the requirements for a particular system.  The
default i8253Timer driver configuration will be appropriate for most
systems, but the optional configuration macros may not be appropriate for
every system.

.IP
The macros SYS_CLK_RATE_MIN, SYS_CLK_RATE_MAX, AUX_CLK_RATE_MIN, and
AUX_CLK_RATE_MAX must be defined to provide parameter checking for the
sys[Aux]ClkRateSet() routines.

.IP
The macro PIT_CLOCK must also be defined to indicate the clock frequency
of the i8253.

.IP
The default configuration implements the system clock through the
programmable timer channel 0.  The real time clock (based on the Motorola
MC146818) is used as the auxiliary clock.

The i8253Timer driver can be configured to use the programmable timer
channel 1 (instead of the real time clock) for the auxiliary clock device.
The BSP does not predefine such a configuration.  However, the driver can
be easily configured to use channel 1 for the auxiliary timer, provided the
user defines the appropriate items in the BSP.  For reasons noted above,
please consult the target system documentation prior to implementing
the auxiliary clock via timer channel 1.

In order to configure i8253Timer to use timer 1 as the auxiliary clock,
the following items must be defined in the BSP:

    (1) Define the manifest constant PIT1_FOR_AUX in config.h.  This constant
        has no associated value.  By defining it, the driver will attempt to
        use timer channel 1 as the auxiliary clock.

    (2) Define the manifest constant PIT1_INT_LVL.  This constant should
        specify the interrupt level (specifically, the IRQ number) associated
        with the output from timer channel 1.  See the definitions of
        PIT0_INT_LVL in the BSP config.h and pc.h files for an example of how
        to do this.

    (3) Connect an interrupt handler to service the auxiliary clock interrupt
        in sysHwInit2().  Existing code in sysHwInit2() will illustrate how to
        install the ISR.  The following code fragment should be sufficient:

.CS
    ...
    #ifdef PIT1_FOR_AUX
    intConnect (INUM_TO_IVEC (INT_NUM_GET (PIT1_INT_LVL)), sysAuxClkInt, 0);
    #endif
    ...
.CE

.IP
This driver includes a timestamp driver; to use this
feature, the macro INCLUDE_TIMESTAMP must be defined in config.h.

.IP "loApicTimer"
This library contains routines to manipulate the timer functions on the
Intel P6 (PentiumPro, II, and III) and P7 (Pentium4) family processor's 
Local APIC/xAPIC Timer with a board-independent interface.
This library handles both the system clock and the auxiliary clock 
functions.  The auxiliary clock is either the RTC (real time clock) or
PIT (programmable interrupt timer) channel 0 (define PIT0_FOR_AUX in 
config.h).

.IP
The macro APIC_TIMER_CLOCK_HZ must also be defined to indicate the clock 
frequency of the Local APIC/xAPIC Timer.

.IP "i8259Intr"
Driver for the Intel 8259A Programmable Interrupt Controller (PIC).

.IP "loApicIntr" and "loApicIntrShow"
Driver for the Intel P6 (PentiumPro, II, III) and P7 (Pentium4) 
family processor's Local APIC/xAPIC.
This driver is used in either Virtual Wire Mode (define VIRTUAL_WIRE_MODE
in config.h) or Symmetric IO Mode (define SYMMETRIC_IO_MODE in config.h).
loApicInit () initializes the Local APIC/xAPIC and scans certain memory
regions as specified in the specification to determine the base
addresses.  It uses LOAPIC_BASE and IOAPIC_BASE defined in the BSP, if
it is not able to find the addresses in the MP configuration table.
Scanned memory regions are defined by two pairs of macro in pc.h,
BIOS_ROM_START and BIOS_ROM_END, EBDA_START and EBDA_END.

.IP "ioApicIntr" and "ioApicIntrShow"
Driver for the Intel P6 (PentiumPro, II, III) and P7 (Pentium4) 
family processor's IO APIC/xAPIC.
This driver is used in Symmetric IO Mode (define SYMMETRIC_IO_MODE in
config.h).  ioApicInit() initializes the IO APIC/xAPIC with information 
stored in redTable[].  redTable[] has three entries - lsw, vectorNo, mask.  
First entry, lsw, stores the least significant word of the IO APIC/xAPIC's 
redirection table.  That includes Trigger Mode, Interrupt Input Pin 
Polarity, Destination Mode, Delivery Mode.  Second entry, vectorNo, is
the vectorNo of the redirection table.  Third entry, mask, should be 0 
and used by ioApicIntLock() and ioApicIntUnlock() to hold the interrupt
mask status.

.IP "nullNvRam"
This library contains dummy non-volatile RAM manipulation routines for targets
lacking non-volatile RAM.  Read and write routines that return ERROR
are included.

The macro NV_RAM_SIZE should be defined as NONE for targets lacking
non-volatile RAM.

.IP "nullVme"
This library contains null routines for boards which do not include any
common bus routines.

.IP "pcmciaLib and pcmciaShow"
Drivers for PCMCIA. In order to use any PCMCIA card 
the INCLUDE_PCMCIA directive
must be enabled in config.h. These drivers currently
support three cards. To use an ATA PC card, enable
INCLUDE_ATA; to use an SRAM PC card, enable INCLUDE_SRAM;
to use a 3COM Etherlink III PC card, enable INCLUDE_ELT.
By default, all three cards are enabled when INCLUDE_PCMCIA is enabled.

.SS "Memory Maps"
.TS
center allbox;
c c c
l l l.
Start Address	Size	Use
0x0	0xa0000	lower memory
0xa0000	0x60000	video ram, etc
0x100000	sysPhysMemTop() - 0x100000	upper memory
.TE

.SS "Shared Memory"
Not applicable to this BSP

.SS "Interrupts"
All ISA interrupts are external to the CPU and are routed
through the ISA interrupt prioritization hardware.  This hardware is
comprised of two 82C59 PICs.  There are 16 ISA interrupts and
interrupt priority levels numbered 0 through 15. The mapping between
interrupt numbers and priority levels is not necessarily one to one.
The motherboard hardware determines the mapping of interrupt
request lines (IRQ) to priority levels. The hardware should
adhere to the standard ISA assignments:

.ne 18 
            IRQ         Priority
            ---         --------
             0              0
             1              1
             2              2
             3             11
             4             12
             5             13
             6             14
             7             15
             8              3
             9              4
            10              5
            11              6
            12              7
            13              8
            14              9
            15             10

IRQs 0 - 7 are handled by PIC1 and IRQs 8 - 15 by PIC2.  PIC2 interrupts are
cascaded into PIC1 at IRQ2 which is reflected in the above table.
The Fully Nested Mode is used in the default configuration of this BSP.

Fully Nested Mode.
In this mode, interrupt requests are ordered in priority
from 0 through 7 (0 is the highest).  When an interrupt is acknowledged the
highest priority request is determined and its vector is placed on the bus.
Additionally, a bit of the Interrupt Service (IS) register is set.  This bit
remains set until the microprocessor issues an EOI command immediately before
returning from the service routine.  While the IS bit is set, all further
interrupts of the same or lower priority are inhibited, while higher level
interrupts are allowed.  The PICs in a PC typically operate in this mode
(normal nested mode).  In this mode, while the slave PIC is being
serviced by the master PIC, the slave PIC blocks all higher priority
interrupt requests.  Alternatively, to allow interrupts of a higher priority,
enable the Special Fully Nested Mode.

Special Fully Nested Mode: define PIC_SPECIAL_FULLY_NESTED_MODE.
This mode is similar to the Fully Nested Mode with the following exceptions:
1) When an interrupt request from a slave PIC is in service, the slave is
not locked out from the master's priority logic and further interrupt
requests from higher priority IRs within the slave will be recognized by
the master and will initiate interrupts to the processor.  2) When exiting
the interrupt service routine, the software must check whether or not the
interrupt serviced was the only interrupt request from the slave.  If it
was the only interrupt request, a non-specific EOI is sent to the master.
If not, no EOI is sent.