📄 archdefs.h
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#define S_Config1WR 3 /* Denotes watch registers present (R) */
#define M_Config1WR (0x1 << S_Config1WR)
#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */
#define M_Config1CA (0x1 << S_Config1CA)
#define S_Config1EP 1 /* Denotes EJTAG present (R) */
#define M_Config1EP (0x1 << S_Config1EP)
#define S_Config1FP 0 /* Denotes floating point present (R) */
#define M_Config1FP (0x1 << S_Config1FP)
#define M_Config10Fields 0x00000060
#define M_Config1RFields 0x7fffff9f
/*
* The following macro generates a table that is indexed
* by the Icache or Dcache sets field in Config1 and
* contains the decoded value of sets per way
*/
#define Config1CacheSets() \
HALF(64); \
HALF(128); \
HALF(256); \
HALF(512); \
HALF(1024); \
HALF(2048); \
HALF(4096); \
HALF(8192);
/*
* The following macro generates a table that is indexed
* by the Icache or Dcache line size field in Config1 and
* contains the decoded value of the cache line size, in bytes
*/
#define Config1CacheLineSize() \
HALF(0); \
HALF(4); \
HALF(8); \
HALF(16); \
HALF(32); \
HALF(64); \
HALF(128); \
HALF(256);
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| | | | | | | | | | | | |S|T| Config1
* | | | | | | | | | | | | | |M|L|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_Config2 $16,2
#define R_C0_Config2 16
#define S_Config2More 31 /* Additional Config registers present (R) */
#define M_Config2More (0x1 << S_Config2More)
#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */
#define M_Config2SM (0x1 << S_Config2SM)
#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */
#define M_Config2TL (0x1 << S_Config2TL)
#define M_Config20Fields 0xfffffffc
#define M_Config2RFields 0x00000003
/*
************************************************************************
* L L A D D R R E G I S T E R ( 1 7 ) *
************************************************************************
*
* 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | // LL Physical Address | LLAddr
* +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_LLAddr $17
#define R_C0_LLAddr 17
#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */
#define M_LLAddr0Fields 0x00000000
#define M_LLAddrRFields 0x00000000
#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000)
#define M_LLAddrRFields64 UNS64Const(0x0000000000000000)
/*
************************************************************************
* W A T C H L O R E G I S T E R ( 1 8 ) *
************************************************************************
*
* 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | // Watch Virtual Address |I|R|W| WatchLo
* +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_WatchLo $18
#define R_C0_WatchLo 18
#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */
#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */
#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr)
#define S_WatchLoI 2 /* Enable Istream watch (R/W) */
#define M_WatchLoI (0x1 << S_WatchLoI)
#define S_WatchLoR 1 /* Enable data read watch (R/W) */
#define M_WatchLoR (0x1 << S_WatchLoR)
#define S_WatchLoW 0 /* Enable data write watch (R/W) */
#define M_WatchLoW (0x1 << S_WatchLoW)
#define M_WatchLo0Fields 0x00000000
#define M_WatchLoRFields 0x00000000
#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000)
#define M_WatchLoRFields64 UNS64Const(0x0000000000000000)
#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW)
/*
************************************************************************
* W A T C H H I R E G I S T E R ( 1 9 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_WatchHi $19
#define R_C0_WatchHi 19
#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */
#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */
#define M_WatchHiM (0x1 << S_WatchHiM)
#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */
#define M_WatchHiG (0x1 << S_WatchHiG)
#define S_WatchHiASID 16 /* ASID value to match (R/W) */
#define M_WatchHiASID (0xff << S_WatchHiASID)
#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */
#define M_WatchHiMask (0x1ff << S_WatchHiMask)
#define M_WatchHi0Fields 0x3f00f007
#define M_WatchHiRFields 0x80000000
/*
************************************************************************
* X C O N T E X T R E G I S T E R ( 2 0 ) *
************************************************************************
*
* 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | // PTEBase | R | BadVPN2<39:13> | 0 | XContext
* +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_XContext $20
#define R_C0_XContext 20
#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */
#define S_XContextBadVPN2 4 /* BadVPN2 (R) */
#define S_XContextBadVPN S_XContextBadVPN2
#define M_XContext0Fields 0x0000000f
/*
************************************************************************
* D E B U G R E G I S T E R ( 2 3 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D|
* |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S|
* |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S|
* | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug
* | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | |
* | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | |
* | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | |
* | | | | | | | | | | | | |r|r| | | | | | | | | | | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_Debug $23 /* EJTAG */
#define R_C0_Debug 23
#define S_DebugDBD 31 /* Debug branch delay (R) */
#define M_DebugDBD (0x1 << S_DebugDBD)
#define S_DebugDM 30 /* Debug mode (R) */
#define M_DebugDM (0x1 << S_DebugDM)
#define S_DebugNoDCR 29 /* No debug control register present (R) */
#define M_DebugNoDCR (0x1 << S_DebugNoDCR)
#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */
#define M_DebugLSNM (0x1 << S_DebugLSNM)
#define S_DebugDoze 27 /* Doze (R) */
#define M_DebugDoze (0x1 << S_DebugDoze)
#define S_DebugHalt 26 /* Halt (R) */
#define M_DebugHalt (0x1 << S_DebugHalt)
#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */
#define M_DebugCountDM (0x1 << S_DebugCountDM)
#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */
#define M_DebugIBusEP (0x1 << S_DebugIBusEP)
#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */
#define M_DebugMCheckP (0x1 << S_DebugMCheckP)
#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */
#define M_DebugCacheEP (0x1 << S_DebugCacheEP)
#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */
#define M_DebugDBusEP (0x1 << S_DebugDBusEP)
#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */
#define M_DebugIEXI (0x1 << S_DebugIEXI)
#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */
#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr)
#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */
#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr)
#define S_DebugEJTAGver 15 /* EJTAG version number (R) */
#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver)
#define S_DebugDExcCode 10 /* Debug exception code (R) */
#define M_DebugDExcCode (0x1f << S_DebugDExcCode)
#define S_DebugNoSSt 9 /* No single step implemented (R) */
#define M_DebugNoSSt (0x1 << S_DebugNoSSt)
#define S_DebugSSt 8 /* Single step enable (R/W) */
#define M_DebugSSt (0x1 << S_DebugSSt)
#define S_DebugDINT 5 /* Debug interrupt (R) */
#define M_DebugDINT (0x1 << S_DebugDINT)
#define S_DebugDIB 4 /* Debug instruction break (R) */
#define M_DebugDIB (0x1 << S_DebugDIB)
#define S_DebugDDBS 3 /* Debug data break store (R) */
#define M_DebugDDBS (0x1 << S_DebugDDBS)
#define S_DebugDDBL 2 /* Debug data break load (R) */
#define M_DebugDDBL (0x1 << S_DebugDDBL)
#define S_DebugDBp 1 /* Debug breakpoint (R) */
#define M_DebugDBp (0x1 << S_DebugDBp)
#define S_DebugDSS 0 /* Debug single step (R) */
#define M_DebugDSS (0x1 << S_DebugDSS)
#define M_Debug0Fields 0x01f000c0
#define M_DebugRFields 0xec0ffe3f
/*
************************************************************************
* D E P C R E G I S T E R ( 2 4 ) *
************************************************************************
*
* 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | // EJTAG Debug Exception PC | DEPC
* +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_DEPC $24
#define R_C0_DEPC 24
#define M_DEEPC0Fields 0x00000000
#define M_DEEPCRFields 0x00000000
#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000)
#define M_DEEPCRFields64 UNS64Const(0x0000000000000000)
/*
************************************************************************
* P E R F C N T R E G I S T E R ( 2 5 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | | |I| | | |E|
* |M| 0 | Event |E|U|S|K|X| PerfCnt
* | | | | | | | |L|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Event Count | PerfCnt
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_PerfCnt $25
#define R_C0_PerfCnt 25
#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */
#define S_PerfCntM 31 /* More performance counters exist (R) */
#define M_PerfCntM (1 << S_PerfCntM)
#define S_PerfCntEvent 5 /* Enabled event (R/W) */
#define M_PerfCntEvent (0x3f << S_PerfCntEvent)
#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */
#define M_PerfCntIE (1 << S_PerfCntIE)
#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */
#define M_PerfCntU (1 << S_PerfCntU)
#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */
#define M_PerfCntS (1 << S_PerfCntS)
#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */
#define M_PerfCntK (1 << S_PerfCntK)
#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */
#define M_PerfCntEXL (1 << S_PerfCntEXL)
#define M_PerfCnt0Fields 0x7ffff800
#define M_PerfCntRFields 0x80000000
/*
************************************************************************
* E R R C T L R E G I S T E R ( 2 6 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Error Control | ErrCtl
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define C0_ErrCtl $26
#define R_C0_ErrCtl 26
#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */
#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */
#define M_ErrCtl0Fields 0x00000000
#define M_ErrCtlRFields 0x00000000
/*
************************************************************************
* C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 ⌨️ 快捷键说明
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