archdefs.h

在 君正芯片上的mips

#define M_USEG                  (0x1 << S_USEG)
#define K_USEG                  0

#define S_EjtagProbeMem         20
#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
#define K_EjtagProbeMem         0



#else

#define S_KSEG3                 29
#define M_KSEG3                 (0x7 << S_KSEG3)
#define K_KSEG3                 7

#define S_KSSEG                 29
#define M_KSSEG                 (0x7 << S_KSSEG)
#define K_KSSEG                 6

#define S_SSEG                  29
#define M_SSEG                  (0x7 << S_SSEG)
#define K_SSEG                  6

#define S_KSEG1                 29
#define M_KSEG1                 (0x7 << S_KSEG1)
#define K_KSEG1                 5

#define S_KSEG0                 29
#define M_KSEG0                 (0x7 << S_KSEG0)
#define K_KSEG0                 4

#define S_KUSEG                 31
#define M_KUSEG                 (0x1 << S_KUSEG)
#define K_KUSEG                 0

#define S_SUSEG                 31
#define M_SUSEG                 (0x1 << S_SUSEG)
#define K_SUSEG                 0

#define S_USEG                  31
#define M_USEG                  (0x1 << S_USEG)
#define K_USEG                  0

#define K_EjtagLower            0xff200000
#define K_EjtagUpper            0xff3fffff

#define S_EjtagProbeMem         20
#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
#define K_EjtagProbeMem         0

#endif



/*
 *************************************************************************
 *   C A C H E   I N S T R U C T I O N   O P E R A T I O N   C O D E S   *
 *************************************************************************
 */

/*
 * Cache encodings
 */
#define K_CachePriI		0			/* Primary Icache */
#define K_CachePriD		1			/* Primary Dcache */
#define K_CachePriU		1			/* Unified primary */
#define K_CacheTerU		2			/* Unified Tertiary */
#define K_CacheSecU		3			/* Unified secondary */


/*
 * Function encodings
 */
#define S_CacheFunc		2			/* Amount to shift function encoding within 5-bit field */
#define K_CacheIndexInv		0			/* Index invalidate */
#define K_CacheIndexWBInv       0			/* Index writeback invalidate */
#define K_CacheIndexLdTag	1			/* Index load tag */
#define K_CacheIndexStTag	2			/* Index store tag */
#define K_CacheHitInv		4			/* Hit Invalidate */
#define K_CacheFill		5			/* Fill (Icache only) */
#define K_CacheHitWBInv		5			/* Hit writeback invalidate */
#define K_CacheHitWB		6			/* Hit writeback */
#define K_CacheFetchLock	7			/* Fetch and lock */

#define ICIndexInv		((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
#define DCIndexWBInv		((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
#define DCIndexInv		DCIndexWBInv
#define ICIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
#define DCIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
#define ICIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
#define DCIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
#define ICHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
#define DCHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
#define ICFill			((K_CacheFill << S_CacheFunc) | K_CachePriI)
#define DCHitWBInv		((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
#define DCHitWB			((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
#define ICFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
#define DCFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)


/*
 *************************************************************************
 *          P R E F E T C H   I N S T R U C T I O N   H I N T S          *
 *************************************************************************
 */

#define PrefLoad		0
#define PrefStore		1
#define PrefLoadStreamed	4
#define PrefStoreStreamed	5
#define PrefLoadRetained	6
#define PrefStoreRetained	7
#define PrefWBInval		25
#define PrefNudge		25


/*
 *************************************************************************
 *             C P U   R E G I S T E R   D E F I N I T I O N S           *
 *************************************************************************
 */


/*
 *************************************************************************
 *                  S O F T W A R E   G P R   N A M E S                  *
 *************************************************************************
 */

#define zero			 $0
#define AT			 $1
#define v0			 $2
#define v1			 $3
#define a0			 $4
#define a1			 $5
#define a2			 $6
#define a3			 $7
#define t0			 $8
#define t1			 $9
#define t2			$10
#define t3			$11
#define t4			$12
#define t5			$13
#define t6			$14
#define t7			$15
#define s0			$16
#define s1			$17
#define s2			$18
#define s3			$19
#define s4			$20
#define s5			$21
#define s6			$22
#define s7			$23
#define t8			$24
#define t9			$25
#define k0			$26
#define k1			$27
#define gp			$28
#define sp			$29
#define fp			$30
#define ra			$31

/*
 * The following registers are used by the AVP environment and
 * are not part of the normal software definitions.
 */

#ifdef MIPSAVPENV
#define repc			$25			/* Expected exception PC */
#define tid			$30			/* Current test case address */
#endif


/*
 *************************************************************************
 *                  H A R D W A R E   G P R   N A M E S                  *
 *************************************************************************
 *
 * In the AVP environment, several of the `r' names are removed from the
 * name space because they are used by the kernel for special purposes.
 * Removing them causes assembly rather than runtime errors for tests that
 * use the `r' names.
 *
 *	- r25 (repc) is used as the expected PC on an exception
 *	- r26-r27 (k0, k1) are used in the exception handler
 *	- r30 (tid) is used as the current test address
 */

#define r0			 $0
#define r1			 $1
#define r2			 $2
#define r3			 $3
#define r4			 $4
#define r5			 $5
#define r6			 $6
#define r7			 $7
#define r8			 $8
#define r9			 $9
#define r10			$10
#define r11			$11
#define r12			$12
#define r13			$13
#define r14			$14
#define r15			$15
#define r16			$16
#define r17			$17
#define r18			$18
#define r19			$19
#define r20			$20
#define r21			$21
#define r22			$22
#define r23			$23
#define r24			$24
#ifdef MIPSAVPENV
#define r25			r25_unknown
#define r26			r26_unknown
#define r27			r27_unknown
#else
#define r25			$25
#define r26			$26
#define r27			$27
#endif
#define r28			$28
#define r29			$29
#ifdef MIPSAVPENV
#define r30			r30_unknown
#else
#define r30			$30
#endif
#define r31			$31


/*
 *************************************************************************
 *                H A R D W A R E   G P R   I N D I C E S                *
 *************************************************************************
 *
 * These definitions provide the index (number) of the GPR, as opposed
 * to the assembler register name ($n).
 */

#define R_r0			 0
#define R_r1			 1
#define R_r2			 2
#define R_r3			 3
#define R_r4			 4
#define R_r5			 5
#define R_r6			 6
#define R_r7			 7
#define R_r8			 8
#define R_r9			 9
#define R_r10			10
#define R_r11			11
#define R_r12			12
#define R_r13			13
#define R_r14			14
#define R_r15			15
#define R_r16			16
#define R_r17			17
#define R_r18			18
#define R_r19			19
#define R_r20			20
#define R_r21			21
#define R_r22			22
#define R_r23			23
#define R_r24			24
#define R_r25			25
#define R_r26			26
#define R_r27			27
#define R_r28			28
#define R_r29			29
#define R_r30			30
#define R_r31			31
#define R_hi			32			/* Hi register */
#define R_lo			33			/* Lo register */


/*
 *************************************************************************
 *                  S O F T W A R E   G P R   M A S K S                  *
 *************************************************************************
 *
 * These definitions provide the bit mask corresponding to the GPR number
 */

#define M_AT			 (1<<1)
#define M_v0			 (1<<2)
#define M_v1			 (1<<3)
#define M_a0			 (1<<4)
#define M_a1			 (1<<5)
#define M_a2			 (1<<6)
#define M_a3			 (1<<7)
#define M_t0			 (1<<8)
#define M_t1			 (1<<9)
#define M_t2			(1<<10)
#define M_t3			(1<<11)
#define M_t4			(1<<12)
#define M_t5			(1<<13)
#define M_t6			(1<<14)
#define M_t7			(1<<15)
#define M_s0			(1<<16)
#define M_s1			(1<<17)
#define M_s2			(1<<18)
#define M_s3			(1<<19)
#define M_s4			(1<<20)
#define M_s5			(1<<21)
#define M_s6			(1<<22)
#define M_s7			(1<<23)
#define M_t8			(1<<24)
#define M_t9			(1<<25)
#define M_k0			(1<<26)
#define M_k1			(1<<27)
#define M_gp			(1<<28)
#define M_sp			(1<<29)
#define M_fp			(1<<30)
#define M_ra			(1<<31)


/*
 *************************************************************************
 *             C P 0   R E G I S T E R   D E F I N I T I O N S           *
 *************************************************************************
 * Each register has the following definitions:
 *
 *	C0_rrr		The register number (as a $n value)
 *	R_C0_rrr	The register index (as an integer corresponding
 *			to the register number)
 *
 * Each field in a register has the following definitions:
 *
 *	S_rrrfff	The shift count required to right-justify
 *			the field.  This corresponds to the bit
 *			number of the right-most bit in the field.
 *	M_rrrfff	The Mask required to isolate the field.
 *
 * Register diagrams included below as comments correspond to the
 * MIPS32 and MIPS64 architecture specifications.  Refer to other
 * sources for register diagrams for older architectures.
 */


/*
 ************************************************************************
 *                 I N D E X   R E G I S T E R   ( 0 )                  *
 ************************************************************************