📄 ops.h
字号:
REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \} while (0)#define __udc_set_speed_full() \do { \ REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \} while (0)#define __udc_set_speed_low() \do { \ REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \} while (0)#define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM )#define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM )#define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE )#define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE )#define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES )#define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES )#define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK )#define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP )#define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT )#define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT )#define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT )#define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF )#define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US )#define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR )#define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI )#define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC )#define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF )#define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US )#define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR )#define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI )#define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC )#define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF )#define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US )#define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR )#define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI )#define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC )#define __udc_mask_all_dev_intrs() \ ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \ UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC )#define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF )#define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US )#define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR )#define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI )#define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC )#if 0#define __udc_unmask_all_dev_intrs() \ ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \ UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) )#else#define __udc_unmask_all_dev_intrs() \ ( REG_UDC_DevIntMR = 0x00000000 )#endif#define __udc_ep0out_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 )#define __udc_ep5out_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 )#define __udc_ep6out_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 )#define __udc_ep7out_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 )#define __udc_ep0in_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 )#define __udc_ep1in_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 )#define __udc_ep2in_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 )#define __udc_ep3in_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 )#define __udc_ep4in_irq_detected(epintr) \ ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 )#define __udc_mask_ep0out_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) )#define __udc_mask_ep5out_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) )#define __udc_mask_ep6out_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) )#define __udc_mask_ep7out_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) )#define __udc_unmask_ep0out_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) )#define __udc_unmask_ep5out_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) )#define __udc_unmask_ep6out_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) )#define __udc_unmask_ep7out_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) )#define __udc_mask_ep0in_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) )#define __udc_mask_ep1in_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) )#define __udc_mask_ep2in_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) )#define __udc_mask_ep3in_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) )#define __udc_mask_ep4in_irq() \ ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) )#define __udc_unmask_ep0in_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) )#define __udc_unmask_ep1in_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) )#define __udc_unmask_ep2in_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) )#define __udc_unmask_ep3in_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) )#define __udc_unmask_ep4in_irq() \ ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) )#define __udc_mask_all_ep_intrs() \ ( REG_UDC_EPIntMR = 0xffffffff )#define __udc_unmask_all_ep_intrs() \ ( REG_UDC_EPIntMR = 0x00000000 )/* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */#define __udc_config_endpoint_type() \do { \ REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \ REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \} while (0)#define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN )#define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN )#define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN )#define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN )#define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN )#define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN )#define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN )#define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN )#define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F )#define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F )#define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F )#define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F )#define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F )#define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F )#define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F )#define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F )#define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F )#define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F )#define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S )#define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S )#define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S )#define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S )#define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S )#define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S )#define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S )#define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S )#define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S )#define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S )#define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S )#define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S )#define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S )#define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S )#define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S )#define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S )#define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S )#define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S )#define __udc_ep0out_packet_size() \ ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )#define __udc_ep5out_packet_size() \ ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )#define __udc_ep6out_packet_size() \ ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )#define __udc_ep7out_packet_size() \ ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )#define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) )#define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) )#define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) )#define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) )#define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) )#define __udc_ep0out_received_none() \ ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )#define __udc_ep0out_received_data() \ ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )#define __udc_ep0out_received_setup() \ ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )#define __udc_ep5out_received_none() \ ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )#define __udc_ep5out_received_data() \ ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )#define __udc_ep5out_received_setup() \ ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )#define __udc_ep6out_received_none() \ ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )#define __udc_ep6out_received_data() \ ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )#define __udc_ep6out_received_setup() \ ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )#define __udc_ep7out_received_none() \ ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )#define __udc_ep7out_received_data() \ ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )#define __udc_ep7out_received_setup() \ ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )/* ep7out ISO only */#define __udc_ep7out_get_pid() \ ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT )#define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) )#define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) )#define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) )#define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) )#define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) )#define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR )#define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR )#define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR )#define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR )#define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) )#define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) )#define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) )#define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) )#define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) )#define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) )#define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) )#define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) )#define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) )/* set to 0xFFFF for UDC */#define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) )/* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) * c: Configuration number to which this endpoint belongs * i: Interface number to which this endpoint belongs * a: Alternate setting to which this endpoint belongs * p: max Packet size of this endpoint */#define __udc_ep0info_init(c,i,a,p) \do { \ REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \ REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \ REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \ REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \ REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \ REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \ REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \ REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \ REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \ REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \} while (0)#define __udc_ep1info_init(c,i,a,p) \do { \ REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \ REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \ REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \ REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \ REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \ REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \ REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \ REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \ REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \ REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \} while (0)#define __udc_ep2info_init(c,i,a,p) \do { \ REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \ REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \ REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \ REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \ REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \ REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \ REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \ REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \ REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \ REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \} while (0)#define __udc_ep3info_init(c,i,a,p) \do { \ REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \ REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \ REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \ REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \ REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \ REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \ REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \ REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \ REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \ REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \} while (0)#define __udc_ep4info_init(c,i,a,p) \do { \ REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \ REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \ REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \ REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \ REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \ REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \ REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \ REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \ REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \ REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \} while (0)⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -