getrounddata.map.qmsg

SMS4是国内第一个公布的商用分组密码算法

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 13:56:57 2007 " "Info: Processing started: Thu Dec 27 13:56:57 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GetRoundData -c GetRoundData --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GetRoundData -c GetRoundData --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sbox.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sbox.v" { { "Info" "ISGN_ENTITY_NAME" "1 sbox " "Info: Found entity 1: sbox" {  } { { "sbox.v" "" { Text "E:/hbx_sms4/GetRoundData/sbox.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IVRFX_VERI_VAR_DIF_ONLY_IN_CASE" "SBin sbin GetRoundData.v(19) " "Info: (10281) Verilog HDL information at GetRoundData.v(19): variable name \"SBin\" and variable name \"sbin\" should not differ only in case" {  } { { "GetRoundData.v" "" { Text "E:/hbx_sms4/GetRoundData/GetRoundData.v" 19 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_VAR_DIF_ONLY_IN_CASE" "SBout sbout GetRoundData.v(25) " "Info: (10281) Verilog HDL information at GetRoundData.v(25): variable name \"SBout\" and variable name \"sbout\" should not differ only in case" {  } { { "GetRoundData.v" "" { Text "E:/hbx_sms4/GetRoundData/GetRoundData.v" 25 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_VAR_DIF_ONLY_IN_CASE" "Tout tout GetRoundData.v(41) " "Info: (10281) Verilog HDL information at GetRoundData.v(41): variable name \"Tout\" and variable name \"tout\" should not differ only in case" {  } { { "GetRoundData.v" "" { Text "E:/hbx_sms4/GetRoundData/GetRoundData.v" 41 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GetRoundData.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file GetRoundData.v" { { "Info" "ISGN_ENTITY_NAME" "1 GetRoundData " "Info: Found entity 1: GetRoundData" {  } { { "GetRoundData.v" "" { Text "E:/hbx_sms4/GetRoundData/GetRoundData.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "GetRoundData " "Info: Elaborating entity \"GetRoundData\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sbox sbox:sbox0 " "Info: Elaborating entity \"sbox\" for hierarchy \"sbox:sbox0\"" {  } { { "GetRoundData.v" "sbox0" { Text "E:/hbx_sms4/GetRoundData/GetRoundData.v" 28 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram sbox:sbox0\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"sbox:sbox0\|altsyncram:altsyncram_component\"" {  } { { "sbox.v" "altsyncram_component" { Text "E:/hbx_sms4/GetRoundData/sbox.v" 71 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_amq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_amq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_amq " "Info: Found entity 1: altsyncram_amq" {  } { { "db/altsyncram_amq.tdf" "" { Text "E:/hbx_sms4/GetRoundData/db/altsyncram_amq.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_amq sbox:sbox0\|altsyncram:altsyncram_component\|altsyncram_amq:auto_generated " "Info: Elaborating entity \"altsyncram_amq\" for hierarchy \"sbox:sbox0\|altsyncram:altsyncram_component\|altsyncram_amq:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 13:56:58 2007 " "Info: Processing ended: Thu Dec 27 13:56:58 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}