gen_round_key.hif

AES作为新型分组密码算法

Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1760
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
SBOX
# storage
db|Gen_Round_Key.(1).cnf
db|Gen_Round_Key.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SBOX.v
312b658e07f40c0ab394ccdb3a43a
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SBOX:SBOX3
SBOX:SBOX2
SBOX:SBOX1
SBOX:SBOX0
}
# end
# entity
altsyncram
# storage
db|Gen_Round_Key.(2).cnf
db|Gen_Round_Key.(2).cnf
# case_insensitive
# source_file
f:|eda|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
SBOX.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_dj31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
wren_b
-1
1
wren_a
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
rden_b
-1
2
data_b
-1
2
data_a
-1
2
clocken1
-1
2
clocken0
-1
2
clock1
-1
2
byteena_b
-1
2
byteena_a
-1
2
address_b
-1
2
}
# include_file {
f:|eda|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
f:|eda|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
f:|eda|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
f:|eda|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
f:|eda|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
f:|eda|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
f:|eda|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
f:|eda|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
f:|eda|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
f:|eda|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
SBOX:SBOX3|altsyncram:altsyncram_component
SBOX:SBOX2|altsyncram:altsyncram_component
SBOX:SBOX1|altsyncram:altsyncram_component
SBOX:SBOX0|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_dj31
# storage
db|Gen_Round_Key.(3).cnf
db|Gen_Round_Key.(3).cnf
# case_insensitive
# source_file
db|altsyncram_dj31.tdf
ba0a349bcefca9ef93edcfa8fa576f
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
SBOX.hex
22d35c403cfbf56d9a2e43c12edea7
}
# hierarchies {
SBOX:SBOX3|altsyncram:altsyncram_component|altsyncram_dj31:auto_generated
SBOX:SBOX2|altsyncram:altsyncram_component|altsyncram_dj31:auto_generated
SBOX:SBOX1|altsyncram:altsyncram_component|altsyncram_dj31:auto_generated
SBOX:SBOX0|altsyncram:altsyncram_component|altsyncram_dj31:auto_generated
}
# end
# entity
RC
# storage
db|Gen_Round_Key.(4).cnf
db|Gen_Round_Key.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RC.v
102e5e06c9462d0772d9231ec93fa4
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RC:RC
}
# end
# entity
altsyncram
# storage
db|Gen_Round_Key.(5).cnf
db|Gen_Round_Key.(5).cnf
# case_insensitive
# source_file
f:|eda|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
4
PARAMETER_DEC
USR
NUMWORDS_A
16
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
RC.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ca31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
wren_b
-1
1
wren_a
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
rden_b
-1
2
data_b
-1
2
data_a
-1
2
clocken1
-1
2
clocken0
-1
2
clock1
-1
2
byteena_b
-1
2
byteena_a
-1
2
address_b
-1
2
}
# include_file {
f:|eda|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
f:|eda|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
f:|eda|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
f:|eda|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
f:|eda|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
f:|eda|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
f:|eda|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
f:|eda|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
f:|eda|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
f:|eda|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
RC:RC|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_ca31
# storage
db|Gen_Round_Key.(6).cnf
db|Gen_Round_Key.(6).cnf
# case_insensitive
# source_file
db|altsyncram_ca31.tdf
54aaff2b63c8e1d54d8995df9c6578f
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
RC.hex
eddac8e0fcb693eeaf1bbf78bb53fc8
}
# hierarchies {
RC:RC|altsyncram:altsyncram_component|altsyncram_ca31:auto_generated
}
# end
# entity
Gen_Round_Key
# storage
db|Gen_Round_Key.(0).cnf
db|Gen_Round_Key.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Gen_Round_Key.v
a4ee76affce5d4ec2f35dbf4deef97c
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# complete