📄 target_device.h
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#define FN2 0x0004 /* Devide Flash clock by: 2^2 */
#define FN3 0x0008 /* Devide Flash clock by: 2^3 */
#define FN4 0x0010 /* Devide Flash clock by: 2^4 */
#define FN5 0x0020 /* Devide Flash clock by: 2^5 */
#define FSSEL0 0x0040 /* Flash clock select 0 */ /* to distinguish from UART SSELx */
#define FSSEL1 0x0080 /* Flash clock select 1 */
#define FSSEL_0 0x0000 /* Flash clock select: 0 - ACLK */
#define FSSEL_1 0x0040 /* Flash clock select: 1 - MCLK */
#define FSSEL_2 0x0080 /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 0x00C0 /* Flash clock select: 3 - SMCLK */
#define BUSY 0x0001 /* Flash busy: 1 */
#define KEYV 0x0002 /* Flash Key violation flag */
#define ACCVIFG 0x0004 /* Flash Access violation flag */
#define WAIT 0x0008 /* Wait flag for segment write */
#define LOCK 0x0010 /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX 0x0020 /* Flash Emergency Exit */
/************************************************************
* Comparator A
************************************************************/
#define CACTL1_ 0x0059 /* Comparator A Control 1 */
sfrb CACTL1 = CACTL1_;
#define CACTL2_ 0x005A /* Comparator A Control 2 */
sfrb CACTL2 = CACTL2_;
#define CAPD_ 0x005B /* Comparator A Port Disable */
sfrb CAPD = CAPD_;
#define CAIFG 0x01 /* Comp. A Interrupt Flag */
#define CAIE 0x02 /* Comp. A Interrupt Enable */
#define CAIES 0x04 /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON 0x08 /* Comp. A enable */
#define CAREF0 0x10 /* Comp. A Internal Reference Select 0 */
#define CAREF1 0x20 /* Comp. A Internal Reference Select 1 */
#define CARSEL 0x40 /* Comp. A Internal Reference Enable */
#define CAEX 0x80 /* Comp. A Exchange Inputs */
#define CAREF_0 0x00 /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1 0x10 /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2 0x20 /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3 0x30 /* Comp. A Int. Ref. Select 3 : Vt*/
#define CAOUT 0x01 /* Comp. A Output */
#define CAF 0x02 /* Comp. A Enable Output Filter */
#define P2CA0 0x04 /* Comp. A Connect External Signal to CA0 : 1 */
#define P2CA1 0x08 /* Comp. A Connect External Signal to CA1 : 1 */
#define CACTL24 0x10
#define CACTL25 0x20
#define CACTL26 0x40
#define CACTL27 0x80
#define CAPD0 0x01 /* Comp. A Disable Input Buffer of Port Register .0 */
#define CAPD1 0x02 /* Comp. A Disable Input Buffer of Port Register .1 */
#define CAPD2 0x04 /* Comp. A Disable Input Buffer of Port Register .2 */
#define CAPD3 0x08 /* Comp. A Disable Input Buffer of Port Register .3 */
#define CAPD4 0x10 /* Comp. A Disable Input Buffer of Port Register .4 */
#define CAPD5 0x20 /* Comp. A Disable Input Buffer of Port Register .5 */
#define CAPD6 0x40 /* Comp. A Disable Input Buffer of Port Register .6 */
#define CAPD7 0x80 /* Comp. A Disable Input Buffer of Port Register .7 */
/************************************************************
* ADC12
************************************************************/
#define ADC12CTL0_ 0x01A0 /* ADC12 Control 0 */
sfrw ADC12CTL0 = ADC12CTL0_;
#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */
sfrw ADC12CTL1 = ADC12CTL1_;
#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */
sfrw ADC12IFG = ADC12IFG_;
#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */
sfrw ADC12IE = ADC12IE_;
#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */
sfrw ADC12IV = ADC12IV_;
#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
#endif
#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */
sfrw ADC12MEM0 = ADC12MEM0_;
#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */
sfrw ADC12MEM1 = ADC12MEM1_;
#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */
sfrw ADC12MEM2 = ADC12MEM2_;
#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */
sfrw ADC12MEM3 = ADC12MEM3_;
#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */
sfrw ADC12MEM4 = ADC12MEM4_;
#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */
sfrw ADC12MEM5 = ADC12MEM5_;
#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */
sfrw ADC12MEM6 = ADC12MEM6_;
#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */
sfrw ADC12MEM7 = ADC12MEM7_;
#define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */
sfrw ADC12MEM8 = ADC12MEM8_;
#define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */
sfrw ADC12MEM9 = ADC12MEM9_;
#define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */
sfrw ADC12MEM10 = ADC12MEM10_;
#define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */
sfrw ADC12MEM11 = ADC12MEM11_;
#define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */
sfrw ADC12MEM12 = ADC12MEM12_;
#define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */
sfrw ADC12MEM13 = ADC12MEM13_;
#define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */
sfrw ADC12MEM14 = ADC12MEM14_;
#define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */
sfrw ADC12MEM15 = ADC12MEM15_;
#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
#endif
#define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */
sfrb ADC12MCTL0 = ADC12MCTL0_;
#define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */
sfrb ADC12MCTL1 = ADC12MCTL1_;
#define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */
sfrb ADC12MCTL2 = ADC12MCTL2_;
#define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */
sfrb ADC12MCTL3 = ADC12MCTL3_;
#define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */
sfrb ADC12MCTL4 = ADC12MCTL4_;
#define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */
sfrb ADC12MCTL5 = ADC12MCTL5_;
#define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */
sfrb ADC12MCTL6 = ADC12MCTL6_;
#define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */
sfrb ADC12MCTL7 = ADC12MCTL7_;
#define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */
sfrb ADC12MCTL8 = ADC12MCTL8_;
#define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */
sfrb ADC12MCTL9 = ADC12MCTL9_;
#define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */
sfrb ADC12MCTL10 = ADC12MCTL10_;
#define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */
sfrb ADC12MCTL11 = ADC12MCTL11_;
#define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */
sfrb ADC12MCTL12 = ADC12MCTL12_;
#define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */
sfrb ADC12MCTL13 = ADC12MCTL13_;
#define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */
sfrb ADC12MCTL14 = ADC12MCTL14_;
#define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */
sfrb ADC12MCTL15 = ADC12MCTL15_;
#define ADC12SC 0x001 /* ADC12CTL0 */
#define ENC 0x002
#define ADC12TOVIE 0x004
#define ADC12OVIE 0x008
#define ADC12ON 0x010
#define REFON 0x020
#define REF2_5V 0x040
#define MSH 0x080
#define MSC 0x080
#define SHT0_0 0*0x100
#define SHT0_1 1*0x100
#define SHT0_2 2*0x100
#define SHT0_3 3*0x100
#define SHT0_4 4*0x100
#define SHT0_5 5*0x100
#define SHT0_6 6*0x100
#define SHT0_7 7*0x100
#define SHT0_8 8*0x100
#define SHT0_9 9*0x100
#define SHT0_10 10*0x100
#define SHT0_11 11*0x100
#define SHT0_12 12*0x100
#define SHT0_13 13*0x100
#define SHT0_14 14*0x100
#define SHT0_15 15*0x100
#define SHT1_0 0*0x1000
#define SHT1_1 1*0x1000
#define SHT1_2 2*0x1000
#define SHT1_3 3*0x1000
#define SHT1_4 4*0x1000
#define SHT1_5 5*0x1000
#define SHT1_6 6*0x1000
#define SHT1_7 7*0x1000
#define SHT1_8 8*0x1000
#define SHT1_9 9*0x1000
#define SHT1_10 10*0x1000
#define SHT1_11 11*0x1000
#define SHT1_12 12*0x1000
#define SHT1_13 13*0x1000
#define SHT1_14 14*0x1000
#define SHT1_15 15*0x1000
#define ADC12BUSY 0x0001 /* ADC12CTL1 */
#define CONSEQ_0 0*2
#define CONSEQ_1 1*2
#define CONSEQ_2 2*2
#define CONSEQ_3 3*2
#define ADC12SSEL_0 0*8
#define ADC12SSEL_1 1*8
#define ADC12SSEL_2 2*8
#define ADC12SSEL_3 3*8
#define ADC12DIV_0 0*0x20
#define ADC12DIV_1 1*0x20
#define ADC12DIV_2 2*0x20
#define ADC12DIV_3 3*0x20
#define ADC12DIV_4 4*0x20
#define ADC12DIV_5 5*0x20
#define ADC12DIV_6 6*0x20
#define ADC12DIV_7 7*0x20
#define ISSH 0x0100
#define SHP 0x0200
#define SHS_0 0*0x400
#define SHS_1 1*0x400
#define SHS_2 2*0x400
#define SHS_3 3*0x400
#define CSTARTADD_0 0*0x1000
#define CSTARTADD_1 1*0x1000
#define CSTARTADD_2 2*0x1000
#define CSTARTADD_3 3*0x1000
#define CSTARTADD_4 4*0x1000
#define CSTARTADD_5 5*0x1000
#define CSTARTADD_6 6*0x1000
#define CSTARTADD_7 7*0x1000
#define CSTARTADD_8 8*0x1000
#define CSTARTADD_9 9*0x1000
#define CSTARTADD_10 10*0x1000
#define CSTARTADD_11 11*0x1000
#define CSTARTADD_12 12*0x1000
#define CSTARTADD_13 13*0x1000
#define CSTARTADD_14 14*0x1000
#define CSTARTADD_15 15*0x1000
#define INCH_0 0 /* ADC12CTLx */
#define INCH_1 1
#define INCH_2 2
#define INCH_3 3
#define INCH_4 4
#define INCH_5 5
#define INCH_6 6
#define INCH_7 7
#define INCH_8 8
#define INCH_9 9
#define INCH_10 10
#define INCH_11 11
#define INCH_12 12
#define INCH_13 13
#define INCH_14 14
#define INCH_15 15
#define SREF_0 0*0x10
#define SREF_1 1*0x10
#define SREF_2 2*0x10
#define SREF_3 3*0x10
#define SREF_4 4*0x10
#define SREF_5 5*0x10
#define SREF_6 6*0x10
#define SREF_7 7*0x10
#define EOS 0x80
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define BASICTIMER_VECTOR 0 * 2 /* 0xFFE0 Basic Timer */
#define PORT2_VECTOR 1 * 2 /* 0xFFE2 Port 2 */
#define UART1TX_VECTOR 2 * 2 /* 0xFFE4 UART 1 Transmit */
#define UART1RX_VECTOR 3 * 2 /* 0xFFE6 UART 1 Receive */
#define PORT1_VECTOR 4 * 2 /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR 5 * 2 /* 0xFFEA Timer A CC1-2, TA */
#define TIMERA0_VECTOR 6 * 2 /* 0xFFEC Timer A CC0 */
#define ADC_VECTOR 7 * 2 /* 0xFFEE ADC */
#define UART0TX_VECTOR 8 * 2 /* 0xFFF0 UART 0 Transmit */
#define UART0RX_VECTOR 9 * 2 /* 0xFFF2 UART 0 Receive */
#define WDT_VECTOR 10 * 2 /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR 11 * 2 /* 0xFFF6 Comparator A */
#define TIMERB1_VECTOR 12 * 2 /* 0xFFF8 Timer B 1-7 */
#define TIMERB0_VECTOR 13 * 2 /* 0xFFFA Timer B 0 */
#define NMI_VECTOR 14 * 2 /* 0xFFFC Non-maskable */
#define RESET_VECTOR 15 * 2 /* 0xFFFE Reset [Highest Priority] */
/************************************************************
* End of Modules
************************************************************/
#endif /* #ifndef __msp430x44x */
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