target_device.h

TI三相电能表源程序

const sfrb U0RXBUF        = U0RXBUF_;
#define U0TXBUF_            0x0077  /* UART 0 Transmit Buffer */
sfrb    U0TXBUF           = U0TXBUF_;

/* Alternate register names */

#define UCTL0_              0x0070  /* UART 0 Control */
sfrb    UCTL0             = UCTL0_;
#define UTCTL0_             0x0071  /* UART 0 Transmit Control */
sfrb    UTCTL0            = UTCTL0_;
#define URCTL0_             0x0072  /* UART 0 Receive Control */
sfrb    URCTL0            = URCTL0_;
#define UMCTL0_             0x0073  /* UART 0 Modulation Control */
sfrb    UMCTL0            = UMCTL0_;
#define UBR00_              0x0074  /* UART 0 Baud Rate 0 */
sfrb    UBR00             = UBR00_;
#define UBR10_              0x0075  /* UART 0 Baud Rate 1 */
sfrb    UBR10             = UBR10_;
#define RXBUF0_             0x0076  /* UART 0 Receive Buffer */
const sfrb RXBUF0         = RXBUF0_;
#define TXBUF0_             0x0077  /* UART 0 Transmit Buffer */
sfrb    TXBUF0            = TXBUF0_;

#define UCTL_0_             0x0070  /* UART 0 Control */
sfrb    UCTL_0            = UCTL_0_;
#define UTCTL_0_            0x0071  /* UART 0 Transmit Control */
sfrb    UTCTL_0           = UTCTL_0_;
#define URCTL_0_            0x0072  /* UART 0 Receive Control */
sfrb    URCTL_0           = URCTL_0_;
#define UMCTL_0_            0x0073  /* UART 0 Modulation Control */
sfrb    UMCTL_0           = UMCTL_0_;
#define UBR0_0_             0x0074  /* UART 0 Baud Rate 0 */
sfrb    UBR0_0            = UBR0_0_;
#define UBR1_0_             0x0075  /* UART 0 Baud Rate 1 */
sfrb    UBR1_0            = UBR1_0_;
#define RXBUF_0_            0x0076  /* UART 0 Receive Buffer */
const sfrb RXBUF_0        = RXBUF_0_;
#define TXBUF_0_            0x0077  /* UART 0 Transmit Buffer */
sfrb    TXBUF_0           = TXBUF_0_;

/************************************************************
* USART 1
************************************************************/

#define U1CTL_              0x0078  /* UART 1 Control */
sfrb    U1CTL             = U1CTL_;
#define U1TCTL_             0x0079  /* UART 1 Transmit Control */
sfrb    U1TCTL            = U1TCTL_;
#define U1RCTL_             0x007A  /* UART 1 Receive Control */
sfrb    U1RCTL            = U1RCTL_;
#define U1MCTL_             0x007B  /* UART 1 Modulation Control */
sfrb    U1MCTL            = U1MCTL_;
#define U1BR0_              0x007C  /* UART 1 Baud Rate 0 */
sfrb    U1BR0             = U1BR0_;
#define U1BR1_              0x007D  /* UART 1 Baud Rate 1 */
sfrb    U1BR1             = U1BR1_;
#define U1RXBUF_            0x007E  /* UART 1 Receive Buffer */
const sfrb U1RXBUF        = U1RXBUF_;
#define U1TXBUF_            0x007F  /* UART 1 Transmit Buffer */
sfrb    U1TXBUF           = U1TXBUF_;

#define UCTL1_              0x0078  /* UART 1 Control */
sfrb    UCTL1             = UCTL1_;
#define UTCTL1_             0x0079  /* UART 1 Transmit Control */
sfrb    UTCTL1            = UTCTL1_;
#define URCTL1_             0x007A  /* UART 1 Receive Control */
sfrb    URCTL1            = URCTL1_;
#define UMCTL1_             0x007B  /* UART 1 Modulation Control */
sfrb    UMCTL1            = UMCTL1_;
#define UBR01_              0x007C  /* UART 1 Baud Rate 0 */
sfrb    UBR01             = UBR01_;
#define UBR11_              0x007D  /* UART 1 Baud Rate 1 */
sfrb    UBR11             = UBR11_;
#define RXBUF1_             0x007E  /* UART 1 Receive Buffer */
const sfrb RXBUF1         = RXBUF1_;
#define TXBUF1_             0x007F  /* UART 1 Transmit Buffer */
sfrb    TXBUF1            = TXBUF1_;

#define UCTL_1_             0x0078  /* UART 1 Control */
sfrb    UCTL_1            = UCTL_1_;
#define UTCTL_1_            0x0079  /* UART 1 Transmit Control */
sfrb    UTCTL_1           = UTCTL_1_;
#define URCTL_1_            0x007A  /* UART 1 Receive Control */
sfrb    URCTL_1           = URCTL_1_;
#define UMCTL_1_            0x007B  /* UART 1 Modulation Control */
sfrb    UMCTL_1           = UMCTL_1_;
#define UBR0_1_             0x007C  /* UART 1 Baud Rate 0 */
sfrb    UBR0_1            = UBR0_1_;
#define UBR1_1_             0x007D  /* UART 1 Baud Rate 1 */
sfrb    UBR1_1            = UBR1_1_;
#define RXBUF_1_            0x007E  /* UART 1 Receive Buffer */
const sfrb RXBUF_1        = RXBUF_1_;
#define TXBUF_1_            0x007F  /* UART 1 Transmit Buffer */
sfrb    TXBUF_1           = TXBUF_1_;

/************************************************************
* Timer A
************************************************************/

#define TAIV_               0x012E  /* Timer A Interrupt Vector Word */
sfrw    TAIV              = TAIV_;
#define TACTL_              0x0160  /* Timer A Control */
sfrw    TACTL             = TACTL_;
#define TACCTL0_            0x0162  /* Timer A Capture/Compare Control 0 */
sfrw    TACCTL0           = TACCTL0_;
#define TACCTL1_            0x0164  /* Timer A Capture/Compare Control 1 */
sfrw    TACCTL1           = TACCTL1_;
#define TACCTL2_            0x0166  /* Timer A Capture/Compare Control 2 */
sfrw    TACCTL2           = TACCTL2_;
#define TAR_                0x0170  /* Timer A */
sfrw    TAR               = TAR_;
#define TACCR0_             0x0172  /* Timer A Capture/Compare 0 */
sfrw    TACCR0            = TACCR0_;
#define TACCR1_             0x0174  /* Timer A Capture/Compare 1 */
sfrw    TACCR1            = TACCR1_;
#define TACCR2_             0x0176  /* Timer A Capture/Compare 2 */
sfrw    TACCR2            = TACCR2_;

/* Alternate register names */
#define CCTL0_              0x0162  /* Timer A Capture/Compare Control 0 */
sfrw    CCTL0             = CCTL0_;
#define CCTL1_              0x0164  /* Timer A Capture/Compare Control 1 */
sfrw    CCTL1             = CCTL1_;
#define CCTL2_              0x0166  /* Timer A Capture/Compare Control 2 */
sfrw    CCTL2             = CCTL2_;
#define CCR0_               0x0172  /* Timer A Capture/Compare 0 */
sfrw    CCR0              = CCR0_;
#define CCR1_               0x0174  /* Timer A Capture/Compare 1 */
sfrw    CCR1              = CCR1_;
#define CCR2_               0x0176  /* Timer A Capture/Compare 2 */
sfrw    CCR2              = CCR2_;

#define TASSEL2             0x0400  /* unused */        /* to distinguish from UART SSELx */
#define TASSEL1             0x0200  /* Timer A clock source select 0 */
#define TASSEL0             0x0100  /* Timer A clock source select 1 */
#define ID1                 0x0080  /* Timer A clock input devider 1 */
#define ID0                 0x0040  /* Timer A clock input devider 0 */
#define MC1                 0x0020  /* Timer A mode control 1 */
#define MC0                 0x0010  /* Timer A mode control 0 */
#define TACLR               0x0004  /* Timer A counter clear */
#define TAIE                0x0002  /* Timer A counter interrupt enable */
#define TAIFG               0x0001  /* Timer A counter interrupt flag */

#define MC_0                 0*0x10  /* Timer A mode control: 0 - Stop */
#define MC_1                 1*0x10  /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2                 2*0x10  /* Timer A mode control: 2 - Continous up */
#define MC_3                 3*0x10  /* Timer A mode control: 3 - Up/Down */
#define ID_0                 0*0x40  /* Timer A input divider: 0 - /1 */
#define ID_1                 1*0x40  /* Timer A input divider: 1 - /2 */
#define ID_2                 2*0x40  /* Timer A input divider: 2 - /4 */
#define ID_3                 3*0x40  /* Timer A input divider: 3 - /8 */
#define TASSEL_0             0*0x100  /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1             1*0x100  /* Timer A clock source select: 1 - ACLK  */
#define TASSEL_2             2*0x100  /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3             3*0x100  /* Timer A clock source select: 3 - INCLK */

#define CM1                 0x8000  /* Capture mode 1 */
#define CM0                 0x4000  /* Capture mode 0 */
#define CCIS1               0x2000  /* Capture input select 1 */
#define CCIS0               0x1000  /* Capture input select 0 */
#define SCS                 0x0800  /* Capture sychronize */
#define SCCI                0x0400  /* Latched capture signal (read) */
#define CAP                 0x0100  /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2             0x0080  /* Output mode 2 */
#define OUTMOD1             0x0040  /* Output mode 1 */
#define OUTMOD0             0x0020  /* Output mode 0 */
#define CCIE                0x0010  /* Capture/compare interrupt enable */
#define CCI                 0x0008  /* Capture input signal (read) */
#define OUT                 0x0004  /* PWM Output signal if output mode 0 */
#define COV                 0x0002  /* Capture/compare overflow flag */
#define CCIFG               0x0001  /* Capture/compare interrupt flag */

#define OUTMOD_0             0*0x20  /* PWM output mode: 0 - output only */
#define OUTMOD_1             1*0x20  /* PWM output mode: 1 - set */
#define OUTMOD_2             2*0x20  /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3             3*0x20  /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4             4*0x20  /* PWM output mode: 4 - toggle */
#define OUTMOD_5             5*0x20  /* PWM output mode: 5 - Reset */
#define OUTMOD_6             6*0x20  /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7             7*0x20  /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0               0*0x1000  /* Capture input select: 0 - CCIxA */
#define CCIS_1               1*0x1000  /* Capture input select: 1 - CCIxB */
#define CCIS_2               2*0x1000  /* Capture input select: 2 - GND */
#define CCIS_3               3*0x1000  /* Capture input select: 3 - Vcc */
#define CM_0                 0*0x4000  /* Capture mode: 0 - disabled */
#define CM_1                 1*0x4000  /* Capture mode: 1 - pos. edge */
#define CM_2                 2*0x4000  /* Capture mode: 1 - neg. edge */
#define CM_3                 3*0x4000  /* Capture mode: 1 - both edges */

/************************************************************
* Timer B
************************************************************/

#define TBIV_               0x011E  /* Timer B Interrupt Vector Word */
sfrw    TBIV              = TBIV_;
#define TBCTL_              0x0180  /* Timer B Control */
sfrw    TBCTL             = TBCTL_;
#define TBCCTL0_            0x0182  /* Timer B Capture/Compare Control 0 */
sfrw    TBCCTL0           = TBCCTL0_;
#define TBCCTL1_            0x0184  /* Timer B Capture/Compare Control 1 */
sfrw    TBCCTL1           = TBCCTL1_;
#define TBCCTL2_            0x0186  /* Timer B Capture/Compare Control 2 */
sfrw    TBCCTL2           = TBCCTL2_;
#define TBCCTL3_            0x0188  /* Timer B Capture/Compare Control 3 */
sfrw    TBCCTL3           = TBCCTL3_;
#define TBCCTL4_            0x018A  /* Timer B Capture/Compare Control 4 */
sfrw    TBCCTL4           = TBCCTL4_;
#define TBCCTL5_            0x018C  /* Timer B Capture/Compare Control 5 */
sfrw    TBCCTL5           = TBCCTL5_;
#define TBCCTL6_            0x018E  /* Timer B Capture/Compare Control 6 */
sfrw    TBCCTL6           = TBCCTL6_;
#define TBR_                0x0190  /* Timer B */
sfrw    TBR               = TBR_;
#define TBCCR0_             0x0192  /* Timer B Capture/Compare 0 */
sfrw    TBCCR0            = TBCCR0_;
#define TBCCR1_             0x0194  /* Timer B Capture/Compare 1 */
sfrw    TBCCR1            = TBCCR1_;
#define TBCCR2_             0x0196  /* Timer B Capture/Compare 2 */
sfrw    TBCCR2            = TBCCR2_;
#define TBCCR3_             0x0198  /* Timer B Capture/Compare 3 */
sfrw    TBCCR3            = TBCCR3_;
#define TBCCR4_             0x019A  /* Timer B Capture/Compare 4 */
sfrw    TBCCR4            = TBCCR4_;
#define TBCCR5_             0x019C  /* Timer B Capture/Compare 5 */
sfrw    TBCCR5            = TBCCR5_;
#define TBCCR6_             0x019E  /* Timer B Capture/Compare 6 */
sfrw    TBCCR6            = TBCCR6_;

#define SHR1                0x4000  /* Timer B Compare latch load group 1 */
#define SHR0                0x2000  /* Timer B Compare latch load group 0 */
#define TBCLGRP1            0x4000  /* Timer B Compare latch load group 1 */
#define TBCLGRP0            0x2000  /* Timer B Compare latch load group 0 */
#define CNTL1               0x1000  /* Counter lenght 1 */
#define CNTL0               0x0800  /* Counter lenght 0 */
#define TBSSEL2             0x0400  /* unused */
#define TBSSEL1             0x0200  /* Clock source 1 */
#define TBSSEL0             0x0100  /* Clock source 0 */
#define TBCLR               0x0004  /* Timer B counter clear */
#define TBIE                0x0002  /* Timer B interrupt enable */
#define TBIFG               0x0001  /* Timer B interrupt flag */

#define TBSSEL_0             0*0x0100  /* Clock Source: TBCLK */
#define TBSSEL_1             1*0x0100  /* Clock Source: ACLK  */
#define TBSSEL_2             2*0x0100  /* Clock Source: SMCLK */
#define TBSSEL_3             3*0x0100  /* Clock Source: INCLK */
#define CNTL_0               0*0x0800  /* Counter lenght: 16 bit */
#define CNTL_1               1*0x0800  /* Counter lenght: 12 bit */
#define CNTL_2               2*0x0800  /* Counter lenght: 10 bit */
#define CNTL_3               3*0x0800  /* Counter lenght:  8 bit */
#define SHR_0                0*0x2000  /* Timer B Group: 0 - individually */
#define SHR_1                1*0x2000  /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define SHR_2                2*0x2000  /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define SHR_3                3*0x2000  /* Timer B Group: 3 - 1 group (all) */
#define TBCLGRP_0            0*0x2000  /* Timer B Group: 0 - individually */
#define TBCLGRP_1            1*0x2000  /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define TBCLGRP_2            2*0x2000  /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define TBCLGRP_3            3*0x2000  /* Timer B Group: 3 - 1 group (all) */

/* Additional Timer B Control Register bits are defined in Timer A */

#define SLSHR1              0x0400  /* Compare latch load source 1 */
#define SLSHR0              0x0200  /* Compare latch load source 0 */
#define CLLD1               0x0400  /* Compare latch load source 1 */
#define CLLD0               0x0200  /* Compare latch load source 0 */

#define SLSHR_0              0*0x0200  /* Compare latch load sourec : 0 - immediate */
#define SLSHR_1              1*0x0200  /* Compare latch load sourec : 1 - TBR counts to 0 */
#define SLSHR_2              2*0x0200  /* Compare latch load sourec : 2 - up/down */
#define SLSHR_3              3*0x0200  /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */

#define CLLD_0               0*0x0200  /* Compare latch load sourec : 0 - immediate */
#define CLLD_1               1*0x0200  /* Compare latch load sourec : 1 - TBR counts to 0 */
#define CLLD_2               2*0x0200  /* Compare latch load sourec : 2 - up/down */
#define CLLD_3               3*0x0200  /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */

/*************************************************************
* Flash Memory
*************************************************************/

#define FCTL1_              0x0128  /* FLASH Control 1 */
sfrw    FCTL1             = FCTL1_;
#define FCTL2_              0x012A  /* FLASH Control 2 */
sfrw    FCTL2             = FCTL2_;
#define FCTL3_              0x012C  /* FLASH Control 3 */
sfrw    FCTL3             = FCTL3_;

#define FRKEY               0x9600  /* Flash key returned by read */
#define FWKEY               0xA500  /* Flash key for write */
#define FXKEY               0x3300  /* for use with XOR instruction */

#define ERASE               0x0002  /* Enable bit for Flash segment erase */
#define MERAS               0x0004  /* Enable bit for Flash mass erase */
#define WRT                 0x0040  /* Enable bit for Flash write */
#define BLKWRT              0x0080  /* Enable bit for Flash segment write */
#define SEGWRT              0x0080  /* old definition */ /* Enable bit for Flash segment write */

#define FN0                 0x0001  /* Devide Flash clock by: 2^0 */
#define FN1                 0x0002  /* Devide Flash clock by: 2^1 */