📄 target_device.h
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#define BT_fCLK2_ACLK 0x00
#define BT_fCLK2_ACLK_DIV256 BTDIV
#define BT_fCLK2_MCLK BTSSEL
/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
#define BT_fCLK2_DIV2 0x00 /* fINT = fCLK2:2 (default) */
#define BT_fCLK2_DIV4 BTIP0 /* fINT = fCLK2:4 */
#define BT_fCLK2_DIV8 BTIP1 /* fINT = fCLK2:8 */
#define BT_fCLK2_DIV16 BTIP1+BTIP0 /* fINT = fCLK2:16 */
#define BT_fCLK2_DIV32 BTIP2 /* fINT = fCLK2:32 */
#define BT_fCLK2_DIV64 BTIP2+BTIP0 /* fINT = fCLK2:64 */
#define BT_fCLK2_DIV128 BTIP2+BTIP1 /* fINT = fCLK2:128 */
#define BT_fCLK2_DIV256 BTIP2+BTIP1+BTIP0 /* fINT = fCLK2:256 */
/* Frequency of LCD coded with Bits 3-4 */
#define BT_fLCD_DIV32 0x00 /* fLCD = fACLK:32 (default) */
#define BT_fLCD_DIV64 BTFRFQ0 /* fLCD = fACLK:64 */
#define BT_fLCD_DIV128 BTFRFQ1 /* fLCD = fACLK:128 */
#define BT_fLCD_DIV256 BTFRFQ1+BTFRFQ0 /* fLCD = fACLK:256 */
/* LCD frequency values with fBT=fACLK */
#define BT_fLCD_1K 0x00 /* fACLK:32 (default) */
#define BT_fLCD_512 BTFRFQ0 /* fACLK:64 */
#define BT_fLCD_256 BTFRFQ1 /* fACLK:128 */
#define BT_fLCD_128 BTFRFQ1+BTFRFQ0 /* fACLK:256 */
/* LCD frequency values with fBT=fMCLK */
#define BT_fLCD_31K BTSSEL /* fMCLK:32 */
#define BT_fLCD_15_5K BTSSEL+BTFRFQ0 /* fMCLK:64 */
#define BT_fLCD_7_8K BTSSEL+BTFRFQ1+BTFRFQ0 /* fMCLK:256 */
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
/* fBT=fACLK is thought for longer interval times */
#define BT_ADLY_0_064 0x00 /* 0.064ms interval (default) */
#define BT_ADLY_0_125 BTIP0 /* 0.125ms " */
#define BT_ADLY_0_25 BTIP1 /* 0.25ms " */
#define BT_ADLY_0_5 BTIP1+BTIP0 /* 0.5ms " */
#define BT_ADLY_1 BTIP2 /* 1ms " */
#define BT_ADLY_2 BTIP2+BTIP0 /* 2ms " */
#define BT_ADLY_4 BTIP2+BTIP1 /* 4ms " */
#define BT_ADLY_8 BTIP2+BTIP1+BTIP0 /* 8ms " */
#define BT_ADLY_16 BTDIV /* 16ms " */
#define BT_ADLY_32 BTDIV+BTIP0 /* 32ms " */
#define BT_ADLY_64 BTDIV+BTIP1 /* 64ms " */
#define BT_ADLY_125 BTDIV+BTIP1+BTIP0 /* 125ms " */
#define BT_ADLY_250 BTDIV+BTIP2 /* 250ms " */
#define BT_ADLY_500 BTDIV+BTIP2+BTIP0 /* 500ms " */
#define BT_ADLY_1000 BTDIV+BTIP2+BTIP1 /* 1000ms " */
#define BT_ADLY_2000 BTDIV+BTIP2+BTIP1+BTIP0 /* 2000ms " */
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
/* the timing for short intervals is more precise than ACLK */
/* NOTE */
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
/* Too low interval time results in interrupts too frequent for the processor to handle! */
#define BT_MDLY_0_002 BTSSEL /* 0.002ms interval *** interval times */
#define BT_MDLY_0_004 BTSSEL+BTIP0 /* 0.004ms " *** too short for */
#define BT_MDLY_0_008 BTSSEL+BTIP1 /* 0.008ms " *** interrupt */
#define BT_MDLY_0_016 BTSSEL+BTIP1+BTIP0 /* 0.016ms " *** handling */
#define BT_MDLY_0_032 BTSSEL+BTIP2 /* 0.032ms " */
#define BT_MDLY_0_064 BTSSEL+BTIP2+BTIP0 /* 0.064ms " */
#define BT_MDLY_0_125 BTSSEL+BTIP2+BTIP1 /* 0.125ms " */
#define BT_MDLY_0_25 BTSSEL+BTIP2+BTIP1+BTIP0/* 0.25ms " */
/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
/* this is for BT */
#define BTRESET_CNT1 BTRESET /* BTCNT1 is reset while BTRESET is set */
#define BTRESET_CNT1_2 BTRESET+BTDIV /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
/* this is for BT1 */
#define BTHOLD_CNT1 BTHOLD /* BTCNT1 is held while BTHOLD is set */
#define BTHOLD_CNT1_2 BTHOLD+BTDIV /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
/* INTERRUPT CONTROL BITS */
/* #define BTIE 0x80 */
/* #define BTIFG 0x80 */
/************************************************************
* SYSTEM CLOCK, FLL+
************************************************************/
#define SCFI0_ 0x0050 /* System Clock Frequency Integrator 0 */
sfrb SCFI0 = SCFI0_;
#define FN_2 0x04 /* fDCOCLK = 2*fNominal */
#define FN_3 0x08 /* fDCOCLK = 3*fNominal */
#define FN_4 0x10 /* fDCOCLK = 4.5*fNominal */
#define FN_8 0x20 /* fDCOCLK = 10*fNominal */
#define FLLD0 0x40 /* Loop Divider Bit : 0 */
#define FLLD1 0x80 /* Loop Divider Bit : 1 */
#define FLLD_1 0x00 /* Multiply Selected Loop Freq. By 1 */
#define FLLD_2 0x40 /* Multiply Selected Loop Freq. By 2 */
#define FLLD_4 0x80 /* Multiply Selected Loop Freq. By 4 */
#define FLLD_8 0xC0 /* Multiply Selected Loop Freq. By 8 */
#define SCFI1_ 0x0051 /* System Clock Frequency Integrator 1 */
sfrb SCFI1 = SCFI1_;
#define SCFQCTL_ 0x0052 /* System Clock Frequency Control */
sfrb SCFQCTL = SCFQCTL_;
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
#define SCFQ_64K 0x01 /* fMCLK=2*fACLK 1+1 to 127+1 is possible */
#define SCFQ_128K 0x03 /* fMCLK=4*fACLK */
#define SCFQ_256K 0x07 /* fMCLK=8*fACLK */
#define SCFQ_512K 0x0F /* fMCLK=16*fACLK */
#define SCFQ_1M 0x1F /* fMCLK=32*fACLK */
#define SCFQ_2M 0x3F /* fMCLK=64*fACLK */
#define SCFQ_4M 0x7F /* fMCLK=128*fACLK */
#define SCFQ_M 0x80 /* Modulation Disable */
#define FLL_CTL0_ 0x0053 /* FLL+ Control 0 */
sfrb FLL_CTL0 = FLL_CTL0_;
#define DCOF 0x01 /* DCO Fault Flag */
#define LFOF 0x02 /* Low Frequency Oscillator Fault Flag */
#define XT1OF 0x04 /* High Frequency Oscillator 1 Fault Flag */
#define XT2OF 0x08 /* High Frequency Oscillator 2 Fault Flag */
#define XCAP0PF 0x00 /* XIN Cap = XOUT Cap = 0pf */
#define XCAP10PF 0x10 /* XIN Cap = XOUT Cap = 10pf */
#define XCAP14PF 0x20 /* XIN Cap = XOUT Cap = 14pf */
#define XCAP18PF 0x30 /* XIN Cap = XOUT Cap = 18pf */
#define XTS_FLL 0x40 /* 1: Selects high-freq. oscillator */
#define DCOPLUS 0x80 /* DCO+ Enable */
#define FLL_CTL1_ 0x0054 /* FLL+ Control 1 */
sfrb FLL_CTL1 = FLL_CTL1_;
#define FLL_DIV_1 0x00 /* FLL+ Divide Px.x/ACLK By 1 */
#define FLL_DIV_2 0x01 /* FLL+ Divide Px.x/ACLK By 2 */
#define FLL_DIV_4 0x02 /* FLL+ Divide Px.x/ACLK By 4 */
#define FLL_DIV_8 0x03 /* FLL+ Divide Px.x/ACLK By 8 */
#define SELS 0x04 /* Peripheral Module Clock Source (0: DCO, 1: XT2) */
#define SELM_DCO 0x00 /* Select DCO for CPU MCLK */
#define SELM_XT2 0x10 /* Select XT2 for CPU MCLK */
#define SELM_A 0x18 /* Select A (from LFXT1) for CPU MCLK */
#define XT2OFF 0x20 /* High Frequency Oscillator 2 (XT2) disable */
#define SMCLKOFF 0x40 /* Peripheral Module Clock (SMCLK) disable */
/* INTERRUPT CONTROL BITS */
/* These two bits are defined in the Special Function Registers */
/* #define OFIFG 0x02 */
/* #define OFIE 0x02 */
/************************************************************
* Brown-Out, Supply Voltage Supervision (SVS)
************************************************************/
#define SVSCTL_ 0x0056 /* SVS Control */
sfrb SVSCTL = SVSCTL_;
#define SVSFG 0x01
#define SVSOP 0x02
#define SVSON 0x04
#define PORON 0x08
#define VLDOFF 0x00
#define VLDON 0x10
#define VLD_1_8V 0x10
/************************************************************
* LCD
************************************************************/
#define LCDCTL_ 0x0090 /* LCD Control */
sfrb LCDCTL = LCDCTL_;
/* the names of the mode bits are different from the spec */
#define LCDON 0x01
#define LCDLOWR 0x02
#define LCDSON 0x04
#define LCDMX0 0x08
#define LCDMX1 0x10
#define LCDP0 0x20
#define LCDP1 0x40
#define LCDP2 0x80
/* Display modes coded with Bits 2-4 */
#define LCDSTATIC LCDSON
#define LCD2MUX LCDMX0+LCDSON
#define LCD3MUX LCDMX1+LCDSON
#define LCD4MUX LCDMX1+LCDMX0+LCDSON
/* Group select code with Bits 5-7 Seg.lines Dig.output */
#define LCDSG0 0x00 /* --------- O0 - O23 (default) */
#define LCDSG0_1 LCDP0 /* S0 - S15 O16 - O23 */
#define LCDSG0_2 LCDP1 /* S0 - S19 O20 - O23 */
#define LCDSG0_3 LCDP1+LCDP0 /* S0 - S23 --------- */
#define LCDSG0_4 LCDP2 /* S0 - S23 --------- */
#define LCDSG0_5 LCDP2+LCDP0 /* S0 - S23 --------- */
#define LCDSG0_6 LCDP2+LCDP1 /* S0 - S23 --------- */
#define LCDSG0_7 LCDP2+LCDP1+LCDP0 /* S0 - S23 --------- */
/* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND */
/* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALY MEANS MOV #LCDP1,&LCDCTL! */
#define LCDOG1_7 0x00 /* --------- O0 - O23 (default) */
#define LCDOG2_7 LCDP0 /* S0 - S15 O16 - O23 */
#define LCDOG3_7 LCDP1 /* S0 - S19 O20 - O23 */
#define LCDOG4_7 LCDP1+LCDP0 /* S0 - S23 --------- */
#define LCDOG5_7 LCDP2 /* S0 - S23 --------- */
#define LCDOG6_7 LCDP2+LCDP0 /* S0 - S23 --------- */
#define LCDOG7 LCDP2+LCDP1 /* S0 - S23 --------- */
#define LCDOGOFF LCDP2+LCDP1+LCDP0 /* S0 - S23 --------- */
#define LCDMEM_ 0x0091 /* LCD Memory */
#ifndef __IAR_SYSTEMS_ICC
#define LCDMEM LCDMEM_ /* LCD Memory (for assembler) */
#else
#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
#endif
#define LCDM1_ LCDMEM_ /* LCD Memory 1 */
sfrb LCDM1 = LCDM1_;
#define LCDM2_ 0x0092 /* LCD Memory 2 */
sfrb LCDM2 = LCDM2_;
#define LCDM3_ 0x0093 /* LCD Memory 3 */
sfrb LCDM3 = LCDM3_;
#define LCDM4_ 0x0094 /* LCD Memory 4 */
sfrb LCDM4 = LCDM4_;
#define LCDM5_ 0x0095 /* LCD Memory 5 */
sfrb LCDM5 = LCDM5_;
#define LCDM6_ 0x0096 /* LCD Memory 6 */
sfrb LCDM6 = LCDM6_;
#define LCDM7_ 0x0097 /* LCD Memory 7 */
sfrb LCDM7 = LCDM7_;
#define LCDM8_ 0x0098 /* LCD Memory 8 */
sfrb LCDM8 = LCDM8_;
#define LCDM9_ 0x0099 /* LCD Memory 9 */
sfrb LCDM9 = LCDM9_;
#define LCDM10_ 0x009A /* LCD Memory 10 */
sfrb LCDM10 = LCDM10_;
#define LCDM11_ 0x009B /* LCD Memory 11 */
sfrb LCDM11 = LCDM11_;
#define LCDM12_ 0x009C /* LCD Memory 12 */
sfrb LCDM12 = LCDM12_;
#define LCDM13_ 0x009D /* LCD Memory 13 */
sfrb LCDM13 = LCDM13_;
#define LCDM14_ 0x009E /* LCD Memory 14 */
sfrb LCDM14 = LCDM14_;
#define LCDM15_ 0x009F /* LCD Memory 15 */
sfrb LCDM15 = LCDM15_;
#define LCDM16_ 0x00A0 /* LCD Memory 16 */
sfrb LCDM16 = LCDM16_;
#define LCDM17_ 0x00A1 /* LCD Memory 17 */
sfrb LCDM17 = LCDM17_;
#define LCDM18_ 0x00A2 /* LCD Memory 18 */
sfrb LCDM18 = LCDM18_;
#define LCDM19_ 0x00A3 /* LCD Memory 19 */
sfrb LCDM19 = LCDM19_;
#define LCDM20_ 0x00A4 /* LCD Memory 20 */
sfrb LCDM20 = LCDM20_;
#define LCDMA_ LCDM10_ /* LCD Memory A */
sfrb LCDMA = LCDMA_;
#define LCDMB_ LCDM11_ /* LCD Memory B */
sfrb LCDMB = LCDMB_;
#define LCDMC_ LCDM12_ /* LCD Memory C */
sfrb LCDMC = LCDMC_;
#define LCDMD_ LCDM13_ /* LCD Memory D */
sfrb LCDMD = LCDMD_;
#define LCDME_ LCDM14_ /* LCD Memory E */
sfrb LCDME = LCDME_;
#define LCDMF_ LCDM15_ /* LCD Memory F */
sfrb LCDMF = LCDMF_;
/************************************************************
* USART
************************************************************/
#define PENA 0x80 /* UCTL */
#define PEV 0x40
#define SPB 0x20 /* to distinguish from stackpointer SP */
#define CHAR 0x10
#define LISTEN 0x08
#define SYNC 0x04
#define MM 0x02
#define SWRST 0x01
#define CKPH 0x80 /* UTCTL */
#define CKPL 0x40
#define SSEL1 0x20
#define SSEL0 0x10
#define URXSE 0x08
#define TXWAKE 0x04
#define STC 0x02
#define TXEPT 0x01
#define FE 0x80 /* URCTL */
#define PE 0x40
#define OE 0x20
#define BRK 0x10
#define URXEIE 0x08
#define URXWIE 0x04
#define RXWAKE 0x02
#define RXERR 0x01
/************************************************************
* USART 0
************************************************************/
#define U0CTL_ 0x0070 /* UART 0 Control */
sfrb U0CTL = U0CTL_;
#define U0TCTL_ 0x0071 /* UART 0 Transmit Control */
sfrb U0TCTL = U0TCTL_;
#define U0RCTL_ 0x0072 /* UART 0 Receive Control */
sfrb U0RCTL = U0RCTL_;
#define U0MCTL_ 0x0073 /* UART 0 Modulation Control */
sfrb U0MCTL = U0MCTL_;
#define U0BR0_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb U0BR0 = U0BR0_;
#define U0BR1_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb U0BR1 = U0BR1_;
#define U0RXBUF_ 0x0076 /* UART 0 Receive Buffer */
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