i2saudio.h

EP931X系列的WinCE声卡驱动源代码

//**********************************************************************
//                                                                      
// Filename: i2saudio.h
//                                                                      
// Description: Interface for the I2S codec interface class.
//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
// PARTICULAR PURPOSE.
//
// Use of this source code is subject to the terms of the Cirrus end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to 
// use this source code. For a copy of the EULA, please see the 
// EULA.RTF on your install media.
//
// Copyright(c) Cirrus Logic Corporation 2003, All Rights Reserved                       
//                                                                      
//**********************************************************************

#ifndef _H_I2SAUDIO
#define _H_I2SAUDIO

class I2SCodec : public CodecInterface
{
    public:
        I2SCodec(void);
        virtual MMRESULT Initialize(void );

        virtual MMRESULT    SetVolume
        (
            ULONG ulRightVolume, 
            ULONG ulLeftVolume, 
            ULONG ulChannel
        );

        virtual MMRESULT    SetRecordSampleRate(ULONG ulFrequency, ULONG ulChannel);
        virtual MMRESULT    SetPlaybackSampleRate(ULONG ulFrequency, ULONG ulChannel);
        virtual BOOL        HasSRC(void) { return FALSE; };
        virtual MMRESULT    StartRecord(ULONG ulChannel);
        virtual MMRESULT    StartPlayback(ULONG ulChannel);
        virtual MMRESULT    StopPlayback(ULONG ulChannel);
        virtual MMRESULT    StopRecord(ULONG ulChannel);
        virtual ULONG       GetDmaPort(void);
        virtual ULONG       DmaSampleSize(void) {return 32;}
        virtual             ~I2SCodec(void);
        void                ProducePIOTone(void);

    private:
        MMRESULT            SetSampleRate(ULONG ulFrequency, ULONG ulChannel);
        MMRESULT            WriteCodecReg(UCHAR ucReg, UCHAR usValue);
        MMRESULT            ReadCodecReg(UCHAR ucReg,  PUCHAR pucValue);
        MMRESULT            WriteCodecRegSPI(UCHAR ucRegAddr, UCHAR ucRegValue);
        void                ReadAllCodecReg(void);
        CRITICAL_SECTION    m_CriticalSection;
        ULONG               m_ulM2SClock;
        ULONG               m_ulS2LRClock;
        LARGE_INTEGER       m_PerfFreq;    
        ULONG               m_ulActualFreq;
        ULONG               m_ulCurrentFreq;
        BOOL                m_bTwoWire;
};
//
// CS4228 Register set
//
#define CS4228_DEV_ADDRESS          0x22

#define CS4228_CLOCK_MODE           1
#define CS4228_CHIP_CNTL            2
#define CS4228_ADC_CNTL             3
#define CS4228_DAC_MUTE1            4
#define CS4228_DAC_MUTE2            5
#define CS4228_DAC_DEEMPHASIS       6
#define CS4228_DAC1_VOL             7
#define CS4228_DAC2_VOL             8
#define CS4228_DAC3_VOL             9
#define CS4228_DAC4_VOL             10
#define CS4228_DAC5_VOL             11
#define CS4228_DAC6_VOL             12
#define CS4228_SERIAL_MODE          13
#define CS4228_STATUS               14

#define CLOCK_MODE_BASERATE_128     0x00
#define CLOCK_MODE_BASERATE_256     0x04
#define CLOCK_MODE_BASERATE_384     0x08
#define CLOCK_MODE_BASERATE_512     0x0C
#define CLOCK_MODE_HIGHRATE_64      0x80
#define CLOCK_MODE_HIGHRATE_128     0x84
#define CLOCK_MODE_HIGHRATE_192     0x88
#define CLOCK_MODE_HIGHRATE_256     0x8C

#define CHIP_CNTL_NDIGPN            0x80
#define CHIP_CNTL_ADCPDN            0x10
#define CHIP_CNTL_DACPDN12          0x08
#define CHIP_CNTL_DACPDN34          0x04
#define CHIP_CNTL_DACPDN56          0x02

#define MUTE2_MUTEZ                 0x40
#define MUTE2_MUTEC                 0x80

#define SERIAL_MODE_DCK_MASK        0xC0
#define SERIAL_MODE_DCK_H32         0x80
#define SERIAL_MODE_DCK_H64         0xC0
#define SERIAL_MODE_DCK_B32         0x00
#define SERIAL_MODE_DCK_B48         0x40
#define SERIAL_MODE_DCK_B64         0x80
#define SERIAL_MODE_DCK_B128        0xC0
#define SERIAL_MODE_DMS_MASK        0x30
#define SERIAL_MODE_DMS_SLAVE       0x00
#define SERIAL_MODE_DMS_MASTER      0x30
#define SERIAL_MODE_DDF_RIGHT_24BIT 0x00
#define SERIAL_MODE_DDF_RIGHT_20BIT 0x01
#define SERIAL_MODE_DDF_RIGHT_16BIT 0x02
#define SERIAL_MODE_DDF_LEFT_24BIT  0x03
#define SERIAL_MODE_DDF_MASK        0x07



#endif // _H_I2SAUDIO