cx25871.cpp

EP931X系列的WinCE显示器驱动源代码

//**********************************************************************
//                                                                      
// Filename: CX25871.cpp
//                                                                      
// Description: Routines to Initialize the CX25871 NTSC encoder.
//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
// PARTICULAR PURPOSE.
//
// Use of this source code is subject to the terms of the Cirrus end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to 
// use this source code. For a copy of the EULA, please see the 
// EULA.RTF on your install media.
//
// Copyright(c) Cirrus Logic Corporation 2003, All Rights Reserved                       
//                                                                      
//**********************************************************************
#include <windows.h>
#include "cx25871.h"
#include "hwdefs.h"


//
// A good clock rate for EE is 10KHz.  That's a period of 10 uSec.
// So we have our EE_DELAY that times half a clock period set to 5 uSec.
// Note that for Kittyhawk 100Khz is to fast.
#define EE_DELAY_USEC       100

//
// The number of time we should read the two wire device before giving
// up.
//
#define EE_READ_TIMEOUT     100

static BOOL WriteCX25871Reg(UCHAR ucRegAddr, UCHAR ucRegValue);

//****************************************************************************
// InitializeCX25871640x480
//****************************************************************************
// Initialize the CX25871 for 640x480 NTSC output.
// 
//
void InitializeCX25871For640x480NTSC(void)
{
    //
    // Perform auto-configuration
    //
    WriteCX25871Reg(0xB8, 0);
    // VS_Print( DEST_CONSOLE, "\nAuto-configuration complete for mode 0.\n");
    Sleep(1);

    //                
    // After auto-configuration, setup pseudo-master mode BUT with EN_BLANKO bit cleared
    //
    WriteCX25871Reg(0xBA, CX25871_REGxBA_SLAVER | CX25871_REGxBA_DACOFF);
    WriteCX25871Reg(0xC6, (CX25871_REGxC6_INMODE_MASK & 0x3));
    WriteCX25871Reg(0xC4, CX25871_REGxC4_EN_OUT);
    WriteCX25871Reg(0x32, 0);
    WriteCX25871Reg(0xBA, CX25871_REGxBA_SLAVER );
}



//****************************************************************************
// DelayuS
//****************************************************************************
// Delays a certian number of microseconds.
// 
//
void DelayuS(ULONG ulMicroSec)
{
    LARGE_INTEGER liStart, liCurrent;
    BOOL b;
    b = QueryPerformanceCounter(&liStart);
    //ASSERT(b);
    
    do
    {
        // Sleep(0);
        b = QueryPerformanceCounter(&liCurrent);
        //ASSERT(b);
    } while((liStart.QuadPart + (LONGLONG)ulMicroSec) >=liCurrent.QuadPart);
}


//****************************************************************************
// WriteCX25871Reg
//****************************************************************************
// ucRegAddr    - CS4228 Register Address.
// usRegValue   - CS4228 Register Value.
//
// Return     0 - Success
//            1 - Failure
//

static BOOL WriteCX25871Reg(UCHAR ucRegAddr, UCHAR ucRegValue)
{

    ULONG uiVal, uiDDR;
    unsigned char ucData, ucIdx, ucBit;
    ULONG ulTimeout;

    //FUNC_I2S
    //(
    //    (
    //        L"WriteCX25871Reg: Reg = 0x%02x, Value = 0x%02x\n", 
    //        ucRegAddr, 
    //        ucRegValue
    //    )
    //);

    //
    // Read the current value of the GPIO data and data direction registers.
    //
    uiVal = *GPIO_PGDR;
    uiDDR = *GPIO_PGDDR;

    //
    // If the GPIO pins have not been configured since reset, the data 
    // and clock lines will be set as inputs and with data value of 0.
    // External pullup resisters are pulling them high.
    // Set them both high before configuring them as outputs.
    //
    uiVal |= (GPIOG_EEDAT | GPIOG_EECLK);
    *GPIO_PGDR = uiVal;

    //
    // Delay to meet the EE Interface timing specification.
    //
    DelayuS( EE_DELAY_USEC );

    //
    // Configure the EE data and clock lines as outputs.
    //
    uiDDR |= (GPIOG_EEDAT | GPIOG_EECLK);
    *GPIO_PGDDR = uiDDR;

    //
    // Delay to meet the EE Interface timing specification.
    //
    DelayuS( EE_DELAY_USEC );

    //
    // Drive the EE data line low.  Since the EE clock line is currently
    // high, this is the start condition.
    //
    uiVal &= ~GPIOG_EEDAT;
    *GPIO_PGDR = uiVal;

    //
    // Delay to meet the EE Interface timing specification.
    //
    DelayuS( EE_DELAY_USEC );

    //
    // Drive the EE clock line low.
    //
    uiVal &= ~GPIOG_EECLK;
    *GPIO_PGDR = uiVal;

    //
    // Delay to meet the EE Interface timing specification.
    //
    DelayuS( EE_DELAY_USEC );

    //
    // Loop through the three bytes which we will send.
    //
    for(ucIdx = 0; ucIdx < 3; ucIdx++)
    {
        //
        // Get the appropriate byte based on the current loop iteration.
        //
        if(ucIdx == 0)
        {
            //
            // Since this is a write operation, we set d0 of the address
            // which is the r/w bit.
            //
            ucData = (UCHAR)CX25871_DEV_ADDRESS;
        }
        else if(ucIdx == 1)
        {
            ucData = ucRegAddr;
        }
        else
        {
            ucData = ucRegValue;
        }

        //
        // Loop through the 8 bits in this byte.
        //
        for(ucBit = 0; ucBit < 8; ucBit++)
        {
            //
            // Set the EE data line to correspond to the most significant bit
            // of the data byte.
            // 
            if(ucData & 0x80)
            {
                uiVal |= GPIOG_EEDAT;
            }
            else
            {
                uiVal &= ~GPIOG_EEDAT;
            }
            *GPIO_PGDR = uiVal;

            //
            // Delay to meet the EE Interface timing specification.
            //
            DelayuS( EE_DELAY_USEC );

            //
            // Drive the EE clock line high.
            //
            *GPIO_PGDR = uiVal | GPIOG_EECLK;

            //
            // Delay to meet the EE Interface timing specification.
            //
            DelayuS( EE_DELAY_USEC );

            //
            // Drive the EE clock line low.
            //
            *GPIO_PGDR = uiVal;

            //
            // Delay to meet the EE Interface timing specification.
            //
            DelayuS( EE_DELAY_USEC );

            //
            // Shift the data byte to the left by one bit.
            //
            ucData <<= 1;
        }

        //
        // We've sent the eight bits in this data byte, so we need to wait for
        // the acknowledge from the target.  Reconfigure the EE data line as
        // an input so we can read the acknowledge from the device.
        //
        uiDDR &= ~GPIOG_EEDAT;
        *GPIO_PGDDR = uiDDR;

        //
        // Delay to meet the EE Interface timing specification.
        //
        DelayuS( EE_DELAY_USEC );
    
        //
        // Drive the EE clock line high.
        //
        *GPIO_PGDR = uiVal | GPIOG_EECLK;

        //
        // Delay to meet the EE Interface timing specification.
        //
        DelayuS( EE_DELAY_USEC );

        //
        // Wait until the EE data line is pulled low by the target device.
        //
        ulTimeout = 0;        
        while(*GPIO_PGDR & GPIOG_EEDAT)
        {
            DelayuS( EE_DELAY_USEC );
            ulTimeout++;
            if(ulTimeout > EE_READ_TIMEOUT )
            {
                //ERRMSG
                //((
                //   L"I2SCodec::WriteCodecReg Write timeout on register 0x%02x\r\n",  
                //    (ULONG)ucRegAddr 
                //));
                return 1;
            }
        }

        //
        // Drive the EE clock line low.
        //
        *GPIO_PGDR = uiVal;

        //
        // Delay to meet the EE Interface timing specification.
        //
        DelayuS( EE_DELAY_USEC );
    
        //
        // Reconfigure the EE data line as an output.
        //
        uiDDR |= GPIOG_EEDAT;
        *GPIO_PGDDR = uiDDR;

        //
        // Delay to meet the EE Interface timing specification.
        //
        DelayuS( EE_DELAY_USEC );
    }

    //
    // Drive the EE data line low.
    //
    uiVal &= ~GPIOG_EEDAT;
    *GPIO_PGDR = uiVal;

    //
    // Delay to meet the EE Interface timing specification.
    //
    DelayuS( EE_DELAY_USEC );

    //
    // Drive the EE clock line high.
    //
    uiVal |= GPIOG_EECLK;
    *GPIO_PGDR = uiVal;

    //
    // Delay to meet the EE Interface timing specification.
    //
    DelayuS( EE_DELAY_USEC );

    //
    // Drive the EE data line high.  Since the EE clock line is currently
    // high, this is the stop condition.
    //
    uiVal |= GPIOG_EEDAT;
    *GPIO_PGDR = uiVal;

    //
    // Delay to meet the EE Interface timing specification.
    //
    DelayuS( EE_DELAY_USEC );

    return 0;
}