asm.h

Newlib 嵌入式 C库 标准实现代码

				       "r" (src) : "cc")
#define _mfpr_(procregd, dest) __asm__("mfpr\t" procregd ",%0" : "=r" (dest) : \
				       /* no input */ "0" (dest) : "cc")

/* Multiplication Instructions */
#define _mulsbw_(src, dest)  	__asm__("mulsbw %1,%0" : "=r" (dest) : \
                                   	"r" ((char)src) , "0" (dest))
#define _mulubw_(src, dest)  	__asm__("mulubw %1,%0" : "=r" (dest) : \
                                   	"r" ((unsigned char)src) , "0" (dest))
#define _mulswd_(src, dest)  	__asm__("mulswd %1,%0" : "=r" (dest) : \
                                   	"r" ((short)src) , "0" (dest))
#define _muluwd_(src, dest)  	__asm__("muluwd %1,%0" : "=r" (dest) : \
                                   	"r" ((unsigned short)src) , "0" (dest))
#define _mulb_(src, dest)  	__asm__("mulb %1,%0" : "=r" (dest) : \
					"ri" ((char)src) , "0" (dest))
#define _mulw_(src, dest)  	__asm__("mulw %1,%0" : "=r" (dest) : \
					"ri" ((short)src) , "0" (dest))
#define _muld_(src, dest)  	__asm__("muld %1,%0" : "=r" (dest)  : \
					"ri" ((int)src) , "0" (dest))
#define _mullsd_(hi, lo, src1, src2)  	__asm__("mullsd %2,%3" \
  					: =l (lo), =h (hi) \
					: "r" ((unsigned int)src1) , "r" ((unsigned int)src2))
#define _mullud_(hi, lo, src1, src2)  	__asm__("mullud %2,%3" \
  					: =l (lo), =h (hi) \
					: "r" ((int)src1) , "r" ((int)src2))

/* Q-Format Multiplication Instructions */
#define _mulqb_(src, dest)  	__asm__("mulqb %1,%0" : "=r" (dest) : \
					"r" ((char)src) , "0" (dest))
#define _mulqw_(src, dest)  	__asm__("mulqw %1,%0" : "=r" (dest) : \
					"r" ((short)src) , "0" (dest))

/* nop Instruction */
#define _nop_()  __asm__("nop")

/* Negate Instructions */
#define _negb_(src, dest)  	__asm__("negb %1,%0" : "=r" (dest) : \
					"r" ((char)src) , "0" (dest))
#define _negw_(src, dest)  	__asm__("negw %1,%0" : "=r" (dest) : \
					"r" ((short)src) , "0" (dest))
#define _negd_(src, dest)  	__asm__("negd %1,%0" : "=r" (dest) : \
					"r" ((int)src) , "0" (dest))

/* or Instructions */
#define _orb_(src, dest)  	__asm__("orb %1,%0" : "=r" (dest) : \
                                   "ri" ((unsigned char)src) , "0" (dest))
#define _orw_(src, dest)  	__asm__("orw %1,%0" : "=r" (dest) : \
                                    "ri" ((unsigned short)src) , "0" (dest))
#define _ord_(src, dest)  	__asm__("ord %1,%0" : "=r" (dest)  : \
                                    "ri" ((unsigned int)src) , "0" (dest))

/* Pop 1's Count Instructions */
#define _popcntb_(src, dest)  	__asm__("popcntb %1,%0" : "=r" (dest) : \
					"r" ((char)src) , "0" (dest))
#define _popcntw_(src, dest)  	__asm__("popcntw %1,%0" : "=r" (dest) : \
					"r" ((short)src) , "0" (dest))
#define _popcntd_(src, dest)  	__asm__("popcntd %1,%0" : "=r" (dest)  : \
                                    "r" ((int)src) , "0" (dest))

/* Rotate and Mask Instructions */ 
#define _ram_(shift, end, begin, dest, src) __asm__("ram %1, %2, %3, %0, %4" : \
						    "=r" (dest) : \
						    "i" ((unsigned char) shift), \
						    "i" (end), "i" (begin), \
						    "r" (src), "0" (dest))
#define _rim_(shift, end, begin, dest, src) __asm__("rim %1, %2, %3, %0, %4" : \
						    "=r" (dest) : \
						    "i" ((unsigned char) shift), \
						    "i" (end), "i" (begin), \
						    "r" (src), "0" (dest))

/* retx Instruction */
#define _retx_()  __asm__("retx")

/* Rotate Instructions */
#define _rotb_(shift, dest)  __asm__("rotb %1,%0" : "=r" (dest) : \
				     "i" ((unsigned char)shift) , "0" (dest))
#define _rotw_(shift, dest)  __asm__("rotw %1,%0" : "=r" (dest) : \
				     "i" ((unsigned char)shift) , "0" (dest))
#define _rotd_(shift, dest)  __asm__("rotd %1,%0" : "=r" (dest)  : \
				     "i" ((unsigned char)shift) , "0" (dest))
#define _rotlb_(shift, dest) __asm__("rotlb %1,%0" : "=r" (dest) : \
				     "r" ((unsigned char)shift) , "0" (dest))
#define _rotlw_(shift, dest) __asm__("rotlw %1,%0" : "=r" (dest) : \
				     "r" ((unsigned char)shift) , "0" (dest))
#define _rotld_(shift, dest) __asm__("rotld %1,%0" : "=r" (dest)  : \
				     "r" ((unsigned char)shift) , "0" (dest))
#define _rotrb_(shift, dest) __asm__("rotrb %1,%0" : "=r" (dest) : \
				     "r" ((unsigned char)shift) , "0" (dest))
#define _rotrw_(shift, dest) __asm__("rotrw %1,%0" : "=r" (dest) : \
				     "r" ((unsigned char)shift) , "0" (dest))
#define _rotrd_(shift, dest) __asm__("rotrd %1,%0" : "=r" (dest)  : \
				     "r" ((unsigned char)shift) , "0" (dest))

/* Set Bit Instructions */
#define _sbitb_(pos,dest)  __asm__("sbitb %1,%0" : "=mr" (dest) : \
				   "i" ((unsigned char)pos) , "0" (dest) : "cc")
#define _sbitw_(pos,dest)  __asm__("sbitw %1,%0" : "=mr" (dest) : \
                                   "i" ((unsigned char)pos) , "0" (dest) : "cc")
#define _sbitd_(pos,dest)  __asm__("sbitd %1,%0" : "=mr" (dest) : \
                                   "i" ((unsigned char)pos) , "0" (dest) : "cc")

/* setrfid Instruction */
#define _setrfid_(src)		__asm__("setrfid %0" : /* No output */  : \
					"r" (src) : "cc")

/* Sign Extend Instructions */
#define _sextbw_(src, dest)  	__asm__("sextbw %1,%0" : "=r" (dest) : \
                                   "r" ((char)src) , "0" (dest) )
#define _sextbd_(src, dest)  	__asm__("sextbd %1,%0" : "=r" (dest) : \
                                    "r" ((char)src) , "0" (dest) )
#define _sextwd_(src, dest)  	__asm__("sextwd %1,%0" : "=r" (dest) : \
                                    "r" ((short)src) , "0" (dest) )

/* Shift Left Logical Instructions */
#define _sllb_(src, dest)  	__asm__("sllb %1,%0" : "=r" (dest) : \
					"ri" ((unsigned char)src) , "0" (dest))
#define _sllw_(src, dest)  	__asm__("sllw %1,%0" : "=r" (dest) : \
					"ri" ((unsigned char)src) , "0" (dest))
#define _slld_(src, dest)  	__asm__("slld %1,%0" : "=r" (dest)  : \
					"ri" ((unsigned char)src) , "0" (dest))
/* Shift Right Arithmetic Instructions */
#define _srab_(src, dest)  	__asm__("srab %1,%0" : "=r" (dest) : \
					"ri" ((unsigned char)src) , "0" (dest))
#define _sraw_(src, dest)  	__asm__("sraw %1,%0" : "=r" (dest) : \
					"ri" ((unsigned char)src) , "0" (dest))
#define _srad_(src, dest)  	__asm__("srad %1,%0" : "=r" (dest)  : \
					"ri" ((unsigned char)src) , "0" (dest))

/* Shift Right Logical Instructions */
#define _srlb_(src, dest)  	__asm__("srlb %1,%0" : "=r" (dest) : \
					"ri" ((unsigned char)src) , "0" (dest))
#define _srlw_(src, dest)  	__asm__("srlw %1,%0" : "=r" (dest) : \
					"ri" ((unsigned char)src) , "0" (dest))
#define _srld_(src, dest)  	__asm__("srld %1,%0" : "=r" (dest)  : \
					"ri" ((unsigned char)src) , "0" (dest))
				
/* Store Instructions */
#define _storb_(src,address)  	__asm__("storb %1,%0" : "=m" (address) : \
					"ri" ((unsigned int)src))
#define _storw_(src,address)  	__asm__("storw %1,%0" : "=m" (address) : \
					"ri" ((unsigned int)src))
#define _stord_(src,address)  	__asm__("stord %1,%0" : "=m" (address) : \
					"ri" ((unsigned int)src))

/* Store Multiple Instructions */
#define _storm_(mask, src)  	__asm__("storm %1,%0" : /* No output here */ : \
					"i" (mask) , "r" ((unsigned int)src))
#define _stormp_(mask, src)  	__asm__("stormp %1,%0" : /* No output here */ : \
					"i" (mask) , "r" ((unsigned int)src))

/* Substruct Instructions */
#define _subb_(src, dest)  __asm__("subb	%1, %0" : "=r" (dest) : \
			           "ri" ((unsigned char)src), "0" (dest) : "cc")
#define _subw_(src, dest)  __asm__("subw	%1, %0" : "=r" (dest) : \
			           "ri" ((unsigned short)src), "0" (dest) : "cc")
#define _subd_(src, dest)  __asm__("subd	%1, %0" : "=r" (dest) : \
				   "ri" ((unsigned int)src), "0" (dest) : "cc")

/* Substruct with Carry Instructions */
#define _subcb_(src, dest) __asm__("subcb	%1, %0" : "=r" (dest) : \
			           "ri" ((unsigned char)src), "0" (dest) : "cc")
#define _subcw_(src, dest) __asm__("subcw	%1, %0" : "=r" (dest) : \
				   "ri" ((unsigned short)src), "0" (dest) : "cc")
#define _subcd_(src, dest) __asm__("subcd	%1, %0" : "=r" (dest) : \
			           "ri" ((unsigned int)src), "0" (dest) : "cc")

/* Q-Format Substruct Instructions */
#define _subqb_(src, dest)  	__asm__("subqw %1,%0" : "=r" (dest)  : \
                                        "r" ((char)src) , "0" (dest))
#define _subqw_(src, dest)  	__asm__("subqw %1,%0" : "=r" (dest)  : \
                                        "r" ((short)src) , "0" (dest))
#define _subqd_(src, dest)  	__asm__("subqd %1,%0" : "=r" (dest)  : \
                                        "r" ((short)src) , "0" (dest))

/* Test Bit Instructions */
#define _tbitb_(pos,dest)  __asm__("tbitb %0,%1" : /* No output */ : \
                                   "i" ((unsigned char)pos) , "rm" (dest) : "cc")
#define _tbitw_(pos,dest)  __asm__("tbitw %0,%1" : /* No output */ : \
                                   "i" ((unsigned char)pos) , "rm" (dest) : "cc")
#define _tbitd_(pos,dest)  __asm__("tbitd %0,%1" : /* No output */ : \
                                   "i" ((unsigned char)pos) , "rm" (dest) : "cc")

/* wait Instruction*/
#define _wait_()  		__asm__ volatile ("wait" :  :  : "cc")

/* xor Instructions */
#define _xorb_(src, dest)  	__asm__("xorb %1,%0" : "=r" (dest) : \
                                   "ri" ((unsigned char)src) , "0" (dest))
#define _xorw_(src, dest)  	__asm__("xorw %1,%0" : "=r" (dest) : \
                                    "ri" ((unsigned short)src) , "0" (dest))
#define _xord_(src, dest)  	__asm__("xord %1,%0" : "=r" (dest)  : \
                                    "ri" ((unsigned int)src) , "0" (dest))

/* Zero Extend Instructions */
#define _zextbw_(src, dest)  	__asm__("zextbw %1,%0" : "=r" (dest) : \
					"r" ((unsigned char)src) , "0" (dest))
#define _zextbd_(src, dest)  	__asm__("zextbd %1,%0" : "=r" (dest) : \
					"r" ((unsigned char)src) , "0" (dest))
#define _zextwd_(src, dest)  	__asm__("zextwd %1,%0" : "=r" (dest) : \
					"r" ((unsigned short)src) , "0" (dest))

#define _save_asm_(x) \
  __asm__ volatile (x ::: "memory","cc", \
		    "r0","r1","r2","r3","r4","r5","r6","r7", \
		    "r8","r9","r10","r11","r12","r13")

#endif  /* _ASM */