📄 fpsymbol.h
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; @(#)fpsymbol.h 1.4 90/10/14 20:55:59, Copyright 1989, 1990 AMD ; start of fpsymbol.h file;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Copyright 1989, 1990 Advanced Micro Devices, Inc.;; This software is the property of Advanced Micro Devices, Inc (AMD) which; specifically grants the user the right to modify, use and distribute this; software provided this notice is not removed or altered. All other rights; are reserved by AMD.;; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR; USE OF THIS SOFTWARE.;; So that all may benefit from your experience, please report any problems; or suggestions about this software to the 29K Technical Support Center at; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118.;; Advanced Micro Devices, Inc.; 29K Support Products; Mail Stop 573; 5900 E. Ben White Blvd.; Austin, TX 78741; 800-292-9263;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ______________________________________________________________________;|______________________________________________________________________|;| |;| SYMBOLS FOR DEFINING THE INSTRUCTION WORD |;| |;|______________________________________________________________________|;|______________________________________________________________________|;;; Revision Information:;------------------------------------------------------------------------; Date: March 31, 1989; Author: Roy Carlson per Bob Perlman and Richard Relph;; The symbols section describing transactions was modified to contain; several new symbol values. The reason for the change was to force the ; CA bit to be set--and remain set--once code accesses the coprocessor. ;; Future operating systems will use the Coprocessor Active (CA) bit in ; the Old Processor Status Register to determine whether or not to save; coprocessor state, etc.. This means that the instruction control field ; Set Coprocessor Active (SA) bit should be used as follows:; ; (1) any coprocessor STORE must have its SA bit set to 1, ; so as to set CA,; ; and (2) any coprocessor LOAD must have its SA bit set to 0, ; so as to prevent clearing CA.;------------------------------------------------------------------------; Date: 89/01/30 12:32:13; author: jim; lines added/del: 5/4; Corrected CP_IEEE_GRADUAL_UFLOW_MODE and CP_RMS_MASK.; Added CP_EXCPS_POSITION, the ls bit of the CP_XXX_EXCP ensemble.; fixed a few typos in comments.;------------------------------------------------------------------------; Date: 89/01/23 18:00:26; author: jim; lines added/del: 488/468; Richard O. Parker; January 5, 1989; ; 1) The _cp_prec_field in the "cp_build_inst", "cp_build_inst_h"; and "cp_build_inst_l" macros was not being defined in the case; of Am29K-supported floating-point instructions (e.g., FADD, FSUB,; DADD, etc.).; ; 2) The multiplexor select codes in the opcode table entries; associated with the "cp_build_inst", "cp_build_inst_h" and; "cp_build_inst_l" macros, pertaining to the CONVERT_F_TO_D; and CONVERT_D_TO_F instructions were incorrect.;------------------------------------------------------------------------; Date: 88/12/20 14:28:26; author: jim; lines added/del: 1/1; Larry Westerman corrected definition of CP_MOVE_P.; Version required for Release 1.1 of the Intrinsics shipped 12/12/88.;------------------------------------------------------------------------; Date: 88/11/18 15:44:45; author: law; ; Initial revision;;;========================================================================;; The following mnemonics are used to specify the 14 LSBs of the; instruction word (fields SIP, SIQ, SIT, SIF, IF, and CO).;;========================================================================;; floating point operation codes.; .equ CP_PASS_P, 0x00000000 ; pass P .equ CP_MINUSP, 0x00000040 ; -P .equ CP_ABSP, 0x00000080 ; |P| .equ CP_SIGNT_TIMES_ABSP, 0x00000C00 ; SIGN(T) * |P|; .equ CP_P_PLUS_T, 0x00000001 ; P + T .equ CP_P_MINUS_T, 0x00000101 ; P - T .equ CP_MINUSP_PLUS_T, 0x00001001 ; -P + T .equ CP_MINUSP_MINUS_T, 0x00001101 ; -P - T .equ CP_ABS_P_PLUS_T, 0x00000081 ; |P + T| .equ CP_ABS_P_MINUS_T, 0x00000181 ; |P - T| .equ CP_ABSP_PLUS_ABST, 0x00002201 ; |P| + |T| .equ CP_ABSP_MINUS_ABST, 0x00002301 ; |P| - |T| .equ CP_ABS_ABSP_MINUS_ABST, 0x00002381 ; ||P| - |T||; .equ CP_P_TIMES_Q, 0x00000002 ; P * Q .equ CP_MINUSP_TIMES_Q, 0x00001002 ; -P * Q .equ CP_ABS_P_TIMES_Q, 0x00000082 ; |P * Q|; .equ CP_COMPARE_P_AND_T, 0x00000103 ; compare P and T; .equ CP_MAX_P_AND_T, 0x00000104 ; max P,T .equ CP_MAX_ABSP_AND_ABST, 0x00002304 ; max |P|, |T|; .equ CP_MIN_P_AND_T, 0x00001005 ; min P,T .equ CP_MIN_ABSP_AND_ABST, 0x00003205 ; min |P|,|T| .equ CP_LIMIT_P_TO_MAGT, 0x00003A05 ; limit P to magnitude of T; .equ CP_CONVERT_T_TO_INT, 0x00000006 ; convert T to integer; .equ CP_SCALE_T_TO_INT_BY_Q, 0x00000007 ; scale T to integer by Q; .equ CP_PQ_PLUS_T, 0x00000008 ; (P * Q) + T .equ CP_MINUSPQ_PLUS_T, 0x00001008 ; (-P * Q) + T .equ CP_PQ_MINUS_T, 0x00000108 ; (P * Q) - T .equ CP_MINUSPQ_MINUS_T, 0x00001108 ; (-P * Q) - T .equ CP_ABSPQ_PLUS_ABST, 0x00002A08 ; |(P * Q)| + T .equ CP_MINUSABSPQ_PLUS_ABST, 0x00003A08 ;-|(P * Q)| + T .equ CP_ABSPQ_MINUS_ABST, 0x00002B08 ; |(P * Q)| - |T|; .equ CP_ROUND_T_TO_INT, 0x00000009 ; round T to integral value; .equ CP_RECIPROCAL_OF_P, 0x0000000A ; reciprocal of P; .equ CP_CONVERT_T_TO_ALT, 0x0000000B ; convert T to alt. f.p. format .equ CP_CONVERT_T_FROM_ALT, 0x0000000C ; convert T to alt. f.p. format;;; integer operation codes.; .equ CP_I_PASS_P, 0x00000020 ; integer pass P .equ CP_I_MINUSP, 0x00000060 ; integer -P .equ CP_I_ABSP, 0x000000A0 ; integer |P| .equ CP_I_SIGNT_TIMES_ABSP, 0x00000C20 ; integer SIGN(T) * |P|; .equ CP_I_P_PLUS_T, 0x00000021 ; integer P + T .equ CP_I_P_MINUS_T, 0x00000121 ; integer P - T .equ CP_I_MINUSP_PLUS_T, 0x00001021 ; integer -P + T .equ CP_I_ABS_P_PLUS_T, 0x000000A1 ; integer |P + T| .equ CP_I_ABS_P_MINUS_T, 0x000001A1 ; integer |P - T|; .equ CP_I_P_TIMES_Q, 0x00000022 ; integer P * Q; .equ CP_I_COMPARE_P_AND_T, 0x00000123 ; integer compare P and T; .equ CP_I_MAX_P_AND_T, 0x00000124 ; integer max P,T; .equ CP_I_MIN_P_AND_T, 0x00001025 ; integer min P,T; .equ CP_I_CONVERT_T_TO_FLOAT, 0x00000026 ; integer convert T to f.p.; .equ CP_I_SCALE_T_TO_FLOAT_BY_Q, 0x00000027 ; integer scale T to f.p. by Q; .equ CP_I_P_OR_T, 0x00000030 ; integer P OR T; .equ CP_I_P_AND_T, 0x00000031 ; integer P AND T; .equ CP_I_P_XOR_T, 0x00000032 ; integer P XOR T; .equ CP_I_NOT_T, 0x00000032 ; integer NOT T; .equ CP_I_LSHIFT_P_BY_Q, 0x00000033 ; integer logical shift P by Q; places; .equ CP_I_ASHIFT_P_BY_Q, 0x00000034 ; integer arith. shift P by Q; places; .equ CP_I_FSHIFT_PT_BY_Q, 0x00000035 ; integer funnel shift PT by Q; places;;; move instruction (f.p. or integer); .equ CP_MOVE_P, 0x00000018 ; move operand P;;;========================================================================;; precision codes for the the operands in registers R and S, and for; the result (instruction word fields IPR, RPR).;;========================================================================;; .equ CP_D_S, 0x00008000 ;Double result, single input(s) .equ CP_S_D, 0x00004000 ;Single result, double input(s) .equ CP_D_D, 0x00000000 ;Double result, double input(s) .equ CP_S_S, 0x0000C000 ;Single result, single input(s);;========================================================================;; The following mnemonics are used to specify the 16 LSBs of an Am29027; instruction word for floating-point instructions supported by the; Am29000 instruction set.;;========================================================================; .equ CP_FADD, 0x0000C001 .equ CP_DADD, 0x00000001 .equ CP_FSUB, 0x0000C101 .equ CP_DSUB, 0x00000101 .equ CP_FMUL, 0x0000C002 .equ CP_DMUL, 0x00000002 .equ CP_FEQ, 0x0000C103 .equ CP_DEQ, 0x00000103 .equ CP_FGE, 0x0000C103 .equ CP_DGE, 0x00000103 .equ CP_FGT, 0x0000C103 .equ CP_DGT, 0x00000103 .equ CP_CONVERT_I_TO_F, 0x0000C026 ; CONVERT (int -> s.p.) .equ CP_CONVERT_I_TO_D, 0x00008026 ; CONVERT (int -> d.p.) .equ CP_CONVERT_F_TO_I, 0x0000C006 ; CONVERT (s.p.-> int) .equ CP_CONVERT_D_TO_I, 0x00004006 ; CONVERT (d.p.-> int) .equ CP_CONVERT_F_TO_D, 0x00008000 ; CONVERT (s.p.-> d.p.) .equ CP_CONVERT_D_TO_F, 0x00004000 ; CONVERT (d.p.-> s.p.);;;========================================================================;; operand select codes (instruction word fields PMS, QMS, TMS).;;========================================================================;; .equ CP_P_EQ_R, 0x00000000 .equ CP_P_EQ_S, 0x01000000 .equ CP_P_EQ_0, 0x02000000 .equ CP_P_EQ_ONE_HALF, 0x03000000 .equ CP_P_EQ_IMINUS1, 0x03000000 .equ CP_P_EQ_1, 0x04000000 .equ CP_P_EQ_2, 0x05000000 .equ CP_P_EQ_3, 0x06000000 .equ CP_P_EQ_PI, 0x07000000 .equ CP_P_EQ_IMINUSMAX, 0x07000000 .equ CP_P_EQ_RF0, 0x08000000 .equ CP_P_EQ_RF1, 0x09000000 .equ CP_P_EQ_RF2, 0x0A000000 .equ CP_P_EQ_RF3, 0x0B000000 .equ CP_P_EQ_RF4, 0x0C000000 .equ CP_P_EQ_RF5, 0x0D000000 .equ CP_P_EQ_RF6, 0x0E000000 .equ CP_P_EQ_RF7, 0x0F000000; .equ CP_Q_EQ_R, 0x00000000 .equ CP_Q_EQ_S, 0x00100000 .equ CP_Q_EQ_0, 0x00200000 .equ CP_Q_EQ_ONE_HALF, 0x00300000 .equ CP_Q_EQ_IMINUS1, 0x00300000 .equ CP_Q_EQ_1, 0x00400000 .equ CP_Q_EQ_2, 0x00500000 .equ CP_Q_EQ_3, 0x00600000 .equ CP_Q_EQ_PI, 0x00700000 .equ CP_Q_EQ_IMINUSMAX, 0x00700000 .equ CP_Q_EQ_RF0, 0x00800000 .equ CP_Q_EQ_RF1, 0x00900000 .equ CP_Q_EQ_RF2, 0x00A00000 .equ CP_Q_EQ_RF3, 0x00B00000 .equ CP_Q_EQ_RF4, 0x00C00000 .equ CP_Q_EQ_RF5, 0x00D00000 .equ CP_Q_EQ_RF6, 0x00E00000 .equ CP_Q_EQ_RF7, 0x00F00000; .equ CP_T_EQ_R, 0x00000000 .equ CP_T_EQ_S, 0x00010000 .equ CP_T_EQ_0, 0x00020000 .equ CP_T_EQ_ONE_HALF, 0x00030000 .equ CP_T_EQ_IMINUS1, 0x00030000 .equ CP_T_EQ_1, 0x00040000 .equ CP_T_EQ_2, 0x00050000 .equ CP_T_EQ_3, 0x00060000 .equ CP_T_EQ_PI, 0x00070000 .equ CP_T_EQ_IMINUSMAX, 0x00070000 .equ CP_T_EQ_RF0, 0x00080000 .equ CP_T_EQ_RF1, 0x00090000 .equ CP_T_EQ_RF2, 0x000A0000 .equ CP_T_EQ_RF3, 0x000B0000 .equ CP_T_EQ_RF4, 0x000C0000 .equ CP_T_EQ_RF5, 0x000D0000 .equ CP_T_EQ_RF6, 0x000E0000 .equ CP_T_EQ_RF7, 0x000F0000;;;========================================================================;; destination select codes (instruction word fields RF, RFS);;========================================================================;; .equ CP_DEST_EQ_GP, 0x00000000 .equ CP_DEST_EQ_RF0, 0x80000000 .equ CP_DEST_EQ_RF1, 0x90000000 .equ CP_DEST_EQ_RF2, 0xA0000000 .equ CP_DEST_EQ_RF3, 0xB0000000 .equ CP_DEST_EQ_RF4, 0xC0000000 .equ CP_DEST_EQ_RF5, 0xD0000000 .equ CP_DEST_EQ_RF6, 0xE0000000 .equ CP_DEST_EQ_RF7, 0xF0000000;;; ______________________________________________________________________;|______________________________________________________________________|;| |;| SYMBOLS FOR DEFINING THE MODE REGISTER DOUBLE WORD |;| |;|______________________________________________________________________|;|______________________________________________________________________|;;; .equ CP_PFF_MASK, 0x00000003 ; primary f.p. format mask .equ CP_PFF_EQ_IEEE, 0x00000000 ; primary f.p. format = IEEE .equ CP_PFF_EQ_DECD, 0x00000001 ; primary f.p. format = DEC D .equ CP_PFF_EQ_DECG, 0x00000002 ; primary f.p. format = DEC G .equ CP_PFF_EQ_IBM, 0x00000003 ; primary f.p. format = IBM .equ CP_PFF_POSITION, 0; .equ CP_AFF_MASK, 0x0000000C ; alternate f.p. format mask .equ CP_AFF_EQ_IEEE, 0x00000000 ; alternate f.p. format = IEEE .equ CP_AFF_EQ_DECD, 0x00000004 ; alternate f.p. format = DEC D .equ CP_AFF_EQ_DECG, 0x00000008 ; alternate f.p. format = DEC G .equ CP_AFF_EQ_IBM, 0x0000000C ; alternate f.p. format = IBM .equ CP_AFF_POSITION, 2; .equ CP_SAT_MASK, 0x00000010 ; saturate mode (SAT) mask .equ CP_SATURATE_MODE, 0x00000010 ; enable saturate mode (SAT=1) .equ CP_SAT_POSITION, 4; .equ CP_AP_MASK, 0x00000020 ; affine/proj. mode (AP) mask .equ CP_AFFINE_MODE, 0x00000020 ; enable affine mode (AP=1) .equ CP_PROJECTIVE_MODE, 0x00000000 ; enable projective mode (AP=0) .equ CP_AP_POSITION, 5; .equ CP_TRP_MASK, 0x00000040 ; IEEE trap mode (TRP) mask .equ CP_IEEE_TRAPS_ENABLED, 0x00000040 ; IEEE trap mode enabled (TRP=1) .equ CP_IEEE_TRAPS_DISABLED, 0x00000000 ; IEEE trap mode disabled (TRP=0) .equ CP_TRP_POSITION, 6; .equ CP_SU_MASK, 0x00000080 ; IEEE sud. uflow (SU) mask .equ CP_IEEE_SUDDEN_UFLOW_MODE, 0x00000080 ; IEEE sud. uflow mode (SU=1) .equ CP_IEEE_GRADUAL_UFLOW_MODE,0x00000000 ; IEEE grad uflow mode (SU=0) .equ CP_SU_POSITION, 7; .equ CP_BS_MASK, 0x00000100 ; IBM sig. mask (BS) .equ CP_BS_POSITION, 8; .equ CP_BU_MASK, 0x00000200 ; IBM underflow mask (BU) .equ CP_BU_POSITION, 9; .equ CP_MS_MASK, 0x00000800 ; signed int. mpy (MS) mask .equ CP_SIGNED_INT_MPY_MODE, 0x00000800 ; signed int. mpy mode (MS=1) .equ CP_UNSIGNED_INT_MPY_MODE, 0x00000000 ; unsigned int. mpy mode (MS=0) .equ CP_MS_POSITION, 11; .equ CP_MF_MASK, 0x00003000 ; int. mult. fmt. mode (MF) mask .equ CP_MF_EQ_LSBS, 0x00000000 ; int. mult. fmt. = LSBs .equ CP_MF_EQ_LSBSFA, 0x00001000 ; int. mult. fmt. = LSBs,fmt. adj. .equ CP_MF_EQ_MSBS, 0x00002000 ; int. mult. fmt. = MSBs .equ CP_MF_EQ_MSBSFA, 0x00003000 ; int. mult. fmt. = MSBs,fmt. adj. .equ CP_MF_POSITION, 12; .equ CP_RMS_MASK, 0x0001C000 ; round mode (RMS) mask .equ CP_RMS_EQ_NEAREST, 0x00000000 ; round mode = to nearest .equ CP_RMS_EQ_MINUS_INF, 0x00004000 ; round mode = toward -oo .equ CP_RMS_EQ_PLUS_INF, 0x00008000 ; round mode = toward +oo .equ CP_RMS_EQ_ZERO, 0x0000C000 ; round mode = toward zero .equ CP_RMS_POSITION, 14; .equ CP_PL_MASK, 0x00100000 ; pipeline mode (PL) mask .equ CP_FLOWTHROUGH_MODE, 0x00000000 ; select flow-through mode .equ CP_PIPELINE_MODE, 0x00100000 ; select pipeline mode .equ CP_PL_POSITION, 20; .equ CP_INVALID_OP_EXCP_MASK, 0x00400000 ; invalid operation excp. mask(IM) .equ CP_RESERVED_OP_EXCP_MASK,0x00800000 ; reserved operand excp. mask(RM) .equ CP_OVERFLOW_EXCP_MASK, 0x01000000 ; overflow exception mask (VM) .equ CP_UNDERFLOW_EXCP_MASK, 0x02000000 ; underflow exception mask(UM) .equ CP_INEXACT_EXCP_MASK, 0x04000000 ; inexact result excp. mask(XM) .equ CP_ZERO_EXCP_MASK, 0x08000000 ; zero result exception mask (ZM) .equ CP_EXCPS_POSITION, 22; .equ CP_PLTC_MASK, 0x0000000F ; pipeline timer count (PLTC) mask .equ CP_PLTC_EQ_2, 0x00000002 ; pipeline timer count = 2 .equ CP_PLTC_EQ_3, 0x00000003 ; pipeline timer count = 3 .equ CP_PLTC_EQ_4, 0x00000004 ; pipeline timer count = 4 .equ CP_PLTC_EQ_5, 0x00000005 ; pipeline timer count = 5 .equ CP_PLTC_EQ_6, 0x00000006 ; pipeline timer count = 6 .equ CP_PLTC_EQ_7, 0x00000007 ; pipeline timer count = 7 .equ CP_PLTC_EQ_8, 0x00000008 ; pipeline timer count = 8 .equ CP_PLTC_EQ_9, 0x00000009 ; pipeline timer count = 9 .equ CP_PLTC_EQ_10, 0x0000000A ; pipeline timer count = 10 .equ CP_PLTC_EQ_11, 0x0000000B ; pipeline timer count = 11 .equ CP_PLTC_EQ_12, 0x0000000C ; pipeline timer count = 12 .equ CP_PLTC_EQ_13, 0x0000000D ; pipeline timer count = 13 .equ CP_PLTC_EQ_14, 0x0000000E ; pipeline timer count = 14
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