kernel_cfg.i

免费的OS源代码 符合ITRON4.0规范 http://www.toppers.jp/official_release.html

		
		
		
	



 







 




 




 




 




	

	
	





	

	
	
	





	

	
	
	
	





	

	
	
	
	
	




				

	

	
	
	
	
	
	




				

	

	
	
	
	
	
	
	




				

	

	
	
	
	
	
	
	
	
























 




























 




 

						








 
#pragma define SIL_ENDIAN_LITTLE 0
#pragma define SIL_ENDIAN_BIG 1





 

#pragma define SIL_PRE_LOC BOOL _sil_loc_ = sns_loc()








 
extern void	sil_dly_nse(UINT dlytim) ;



 













 




 


 VB
sil_reb_mem(VP mem)
{
	return(*((volatile VB *) mem));
}

 void
sil_wrb_mem(VP mem, VB data)
{
	*((volatile VB *) mem) = data;
}





 


 VH
sil_reh_mem(VP mem)
{
	return(*((volatile VH *) mem));
}

 void
sil_wrh_mem(VP mem, VH data)
{
	*((volatile VH *) mem) = data;
}











	

	
	








	










 VH
sil_reh_bem(VP mem)
{
	VH	data;

	data = *((volatile VH *) mem);
	return(((VH)((((UH)(data) & 0xff) << 8) | (((UH)(data) >> 8) & 0xff))));
}




 void
sil_wrh_bem(VP mem, VH data)
{
	*((volatile VH *) mem) = ((VH)((((UH)(data) & 0xff) << 8) | (((UH)(data) >> 8) & 0xff)));
}







 

 VW
sil_rew_mem(VP mem)
{
	return(*((volatile VW *) mem));
}

 void
sil_wrw_mem(VP mem, VW data)
{
	*((volatile VW *) mem) = data;
}











	

	
	








	










 VW
sil_rew_bem(VP mem)
{
	VW	data;

	data = *((volatile VW *) mem);
	return(((VW)((((UW)(data) & 0xff) << 24) | (((UW)(data) & 0xff00) << 8) | (((UW)(data)>> 8) & 0xff00) | (((UW)(data) >> 24) & 0xff))));
}




 void
sil_wrw_bem(VP mem, VW data)
{
	*((volatile VW *) mem) = ((VW)((((UW)(data) & 0xff) << 24) | (((UW)(data) & 0xff00) << 8) | (((UW)(data)>> 8) & 0xff00) | (((UW)(data) >> 24) & 0xff)));
}















 





































 
















 










 




 




 


















































 
















 










 




 




 





 




 







 










 




 













 




 





	





	






 





	





	












	

	
	








	













	

	
	








	








 




	





	












	

	
	








	













	

	
	








	

















































 




 






 
#pragma define INT_NO_RST_SW0 1
#pragma define INT_NO_SW1 2
#pragma define INT_NO_UNDEF_SW2 3
#pragma define INT_NO_SW3 4
#pragma define INT_NO_SW4 5
#pragma define INT_NO_SW5 6
#pragma define INT_NO_SW6 7
#pragma define INT_NO_SW7 8
#pragma define INT_NO_NMI 9
#pragma define INT_NO_WD 10
#pragma define INT_NO_0 11
#pragma define INT_NO_1 12
#pragma define INT_NO_2 13
#pragma define INT_NO_3 14
#pragma define INT_NO_4 15
#pragma define INT_NO_5 16
#pragma define INT_NO_6 17
#pragma define INT_NO_7 18
#pragma define INT_NO_8 19
#pragma define INT_NO_TA0 20
#pragma define INT_NO_TA1 21
#pragma define INT_NO_TA2 22
#pragma define INT_NO_TA3 23
#pragma define INT_NO_TA4 24
#pragma define INT_NO_TA5 25
#pragma define INT_NO_TA6 26
#pragma define INT_NO_TA7 27
#pragma define INT_NO_TB00 28
#pragma define INT_NO_TB01 29
#pragma define INT_NO_TB10 30
#pragma define INT_NO_TB11 31
#pragma define INT_NO_TBOF0 32
#pragma define INT_NO_TBOF1 33
#pragma define INT_NO_RX0 34
#pragma define INT_NO_TX0 35
#pragma define INT_NO_RX1 36
#pragma define INT_NO_TX1 37
#pragma define INT_NO_SBI 38
#pragma define INT_NO_RTC 39
#pragma define INT_NO_AD 40
#pragma define INT_NO_TC0 41
#pragma define INT_NO_TC1 42
#pragma define INT_NO_TC2 43
#pragma define INT_NO_TC3 44



 


 
#pragma define TADR_SFR_DMA0V 0x0080
#pragma define TADR_SFR_DMA1V 0x0081
#pragma define TADR_SFR_DMA2V 0x0082
#pragma define TADR_SFR_DMA3V 0x0083
#pragma define TADR_SFR_INTCLR 0x0088
#pragma define TADR_SFR_DMAR 0x0089
#pragma define TADR_SFR_DMAB 0x008a
#pragma define TADR_SFR_IIMC 0x008c
#pragma define TADR_SFR_INTE0AD 0x0090
#pragma define TADR_SFR_INTE12 0x0091
#pragma define TADR_SFR_INTE34 0x0092
#pragma define TADR_SFR_INTE56 0x0093
#pragma define TADR_SFR_INTE78 0x0094
#pragma define TADR_SFR_INTETA01 0x0095
#pragma define TADR_SFR_INTETA23 0x0096
#pragma define TADR_SFR_INTETA45 0x0097
#pragma define TADR_SFR_INTETA67 0x0098
#pragma define TADR_SFR_INTETB0 0x0099
#pragma define TADR_SFR_INTETB1 0x009a
#pragma define TADR_SFR_INTETB01V 0x009b
#pragma define TADR_SFR_INTES0 0x009c
#pragma define TADR_SFR_INTES1 0x009d
#pragma define TADR_SFR_INTSBIRTC 0x009e
#pragma define TADR_SFR_INTETC01 0x00a0
#pragma define TADR_SFR_INTETC23 0x00a1



 
#pragma define TADR_SFR_TA01RUN 0x0100
#pragma define TADR_SFR_TA0REG 0x0102
#pragma define TADR_SFR_TA1REG 0x0103
#pragma define TADR_SFR_TA01MOD 0x0104
#pragma define TADR_SFR_TA1FFCR 0x0105
#pragma define TADR_SFR_TA23RUN 0x0108
#pragma define TADR_SFR_TA2REG 0x010a
#pragma define TADR_SFR_TA3REG 0x010b
#pragma define TADR_SFR_TA23MOD 0x010c
#pragma define TADR_SFR_TA3FFCR 0x010d
#pragma define TADR_SFR_TA45RUN 0x0110
#pragma define TADR_SFR_TA4REG 0x0112
#pragma define TADR_SFR_TA5REG 0x0113
#pragma define TADR_SFR_TA45MOD 0x0114
#pragma define TADR_SFR_TA5FFCR 0x0115
#pragma define TADR_SFR_TA67RUN 0x0118
#pragma define TADR_SFR_TA6REG 0x011a
#pragma define TADR_SFR_TA7REG 0x011b
#pragma define TADR_SFR_TA67MOD 0x011c
#pragma define TADR_SFR_TA7FFCR 0x011d



 
#pragma define TADR_SFR_SC0BUF 0x0200
#pragma define TADR_SFR_SC0CR 0x0201
#pragma define TADR_SFR_SC0MOD0 0x0202
#pragma define TADR_SFR_BR0CR 0x0203
#pragma define TADR_SFR_BR0ADD 0x0204
#pragma define TADR_SFR_SC0MOD1 0x0205
#pragma define TADR_SFR_SIRCR 0x0207
#pragma define TADR_SFR_SC1BUF 0x0208
#pragma define TADR_SFR_SC1CR 0x0209
#pragma define TADR_SFR_SC1MOD0 0x020a
#pragma define TADR_SFR_BR1CR 0x020b
#pragma define TADR_SFR_BR1ADD 0x020c
#pragma define TADR_SFR_SC1MOD1 0x020d
#pragma define TADR_SFR_SBI0CR1 0x0240
#pragma define TADR_SFR_SBI0DBR 0x0241
#pragma define TADR_SFR_I2C0AR 0x0242
#pragma define TADR_SFR_SBI0CR2 0x0243
#pragma define TADR_SFR_SBI0BR0 0x0244
#pragma define TADR_SFR_SBI0BR1 0x0245



 


 
 
#pragma define TBIT_INTM_L 0x07
#pragma define TBIT_INTC_L 0x08
#pragma define TBIT_INTM_H 0x70
#pragma define TBIT_INTC_H 0x80
 
 
#pragma define TBIT_INT0_CLR 0x0a
#pragma define TBIT_INT1_CLR 0x0b
#pragma define TBIT_INT2_CLR 0x0c
#pragma define TBIT_INT3_CLR 0x0d
#pragma define TBIT_INT4_CLR 0x0e
#pragma define TBIT_INT5_CLR 0x0f
#pragma define TBIT_INT6_CLR 0x10
#pragma define TBIT_INT7_CLR 0x11
#pragma define TBIT_INT8_CLR 0x12
#pragma define TBIT_TA0_CLR 0x13
#pragma define TBIT_TA1_CLR 0x14
#pragma define TBIT_TA2_CLR 0x15
#pragma define TBIT_TA3_CLR 0x16
#pragma define TBIT_TA4_CLR 0x17
#pragma define TBIT_TA5_CLR 0x18
#pragma define TBIT_TA6_CLR 0x19
#pragma define TBIT_TA7_CLR 0x1a
#pragma define TBIT_TB00_CLR 0x1b
#pragma define TBIT_TB01_CLR 0x1c
#pragma define TBIT_TB10_CLR 0x1d
#pragma define TBIT_TB11_CLR 0x1e
#pragma define TBIT_TBOF0_CLR 0x1f
#pragma define TBIT_TBOF1_CLR 0x20
#pragma define TBIT_RX0_CLR 0x21
#pragma define TBIT_TX0_CLR 0x22
#pragma define TBIT_RX1_CLR 0x23
#pragma define TBIT_TX1_CLR 0x24
#pragma define TBIT_SBI_CLR 0x25
#pragma define TBIT_RTC_CLR 0x26
#pragma define TBIT_AD_CLR 0x27



 
 
#pragma define TBIT_TA0RUN 0x01
#pragma define TBIT_TA1RUN 0x02
#pragma define TBIT_TA01PRUN 0x04
#pragma define TBIT_I2TA01 0x08
#pragma define TBIT_TA0RDE 0x80
 
#pragma define TBIT_TA0CLK 0x03
#pragma define TBIT_TA0CLK0 0x00
#pragma define TBIT_TA0CLK1 0x01
#pragma define TBIT_TA0CLK4 0x02
#pragma define TBIT_TA0CLK16 0x03
#pragma define TBIT_TA1CLK 0x0c
#pragma define TBIT_TA1CLK0 0x00
#pragma define TBIT_TA1CLK1 0x04
#pragma define TBIT_TA1CLK16 0x08
#pragma define TBIT_TA1CLK256 0x0c
#pragma define TBIT_PWM 0x30
#pragma define TBIT_PWM26 0x10
#pragma define TBIT_PWM27 0x20
#pragma define TBIT_PWM28 0x30
#pragma define TBIT_TA01M 0xc0
#pragma define TBIT_TA01M8 0x00
#pragma define TBIT_TA01M16 0x40
#pragma define TBIT_TA01MPPG 0x80
#pragma define TBIT_TA01MPWM 0xc0



 
 
#pragma define TBIT_SIOSC 0x03
#pragma define TBIT_SIOSCT 0x00
#pragma define TBIT_SIOSCBRG 0x01
#pragma define TBIT_SIOSCFSYS 0x02
#pragma define TBIT_SIOSCSCLK 0x03
#pragma define TBIT_SIOSM 0x0c
#pragma define TBIT_SIOSMIO 0x00
#pragma define TBIT_SIOSMU7 0x04
#pragma define TBIT_SIOSMU8 0x08
#pragma define TBIT_SIOSMU9 0x0c
#pragma define TBIT_SIOWU 0x10
#pragma define TBIT_SIORXE 0x20
#pragma define TBIT_SIOCTSE 0x40
#pragma define TBIT_SIOTB8 0x80
 
#pragma define TBIT_SIOIOC 0x01
#pragma define TBIT_SIOSCLKS 0x02
#pragma define TBIT_SIOFERR 0x04
#pragma define TBIT_SIOPERR 0x08
#pragma define TBIT_SIOOERR 0x10
#pragma define TBIT_SIOPE 0x20
#pragma define TBIT_SIOEVEN 0x40
#pragma define TBIT_SIORB8 0x80
 
#pragma define TBIT_SIOBRS 0x0f
#pragma define TBIT_SIOBRCK 0x30
#pragma define TBIT_SIOBRCK0 0x00
#pragma define TBIT_SIOBRCK2 0x10
#pragma define TBIT_SIOBRCK8 0x20
#pragma define TBIT_SIOBRCK32 0x30
#pragma define TBIT_SIOBRADD 0x40
#pragma define TBIT_SIOBRK 0x0f
 
#pragma define TBIT_SIOFDPX 0x40
#pragma define TBIT_SIOI2S 0x80






 
#pragma define INHNO_TIMER INT_NO_TA0



 
#pragma define INT_LEVEL_TIMER 0x05





 
typedef UH	CLOCK;





 
#pragma define TIMER_CLOCK 125



 
#pragma define MAX_CLOCK ((CLOCK) 0xff)



 
#pragma define GET_TOLERANCE 100





 
#pragma inline hw_timer_initialize

void
hw_timer_initialize()
{
	 
	sil_wrb_mem((VP)0x0100,
		(sil_reb_mem((VP)0x0100) & ~0x01));
	 
	sil_wrb_mem((VP)0x0100,
		(sil_reb_mem((VP)0x0100) | 0x08));
	sil_wrb_mem((VP)0x0104,
		(sil_reb_mem((VP)0x0104) | 0x03));
	sil_wrb_mem((VP)0x0100, 125 );
	 
	sil_wrb_mem((VP)0x0088, 0x13 );
	sil_wrb_mem((VP)0x0095,
		((sil_reb_mem((VP)0x0095) & ~0x07) | 0x05));
	 
	sil_wrb_mem((VP)0x0100,
		(sil_reb_mem((VP)0x0100) | (0x04 | 0x01)));
}



 
#pragma inline hw_timer_int_clear

void
hw_timer_int_clear()
{
	 
	sil_wrb_mem((VP)0x0088, 0x13 );
}





 
#pragma inline hw_timer_terminate

void
hw_timer_terminate()
{
	 
	sil_wrb_mem((VP)0x0100,
		(sil_reb_mem((VP)0x0100) & ~0x01));
}



 
#pragma inline hw_timer_get_current

CLOCK
hw_timer_get_current(void)
{
	return 0;
}



 
#pragma inline hw_timer_fetch_interrupt

BOOL
hw_timer_fetch_interrupt(void)
{
	return (sil_reb_mem((VP)0x0095) & 0x08);
}








































 






 








 
extern void	timer_initialize(VP_INT exinf);



 
extern void	timer_handler(void);





 
extern void	timer_terminate(VP_INT exinf);






































 



 









































 


















 










 




 












































 
















 










 




 




 





 




 







 










 




 













 




 





	





	






 





	





	












	

	
	








	













	

	
	








	








 




	





	












	

	
	








	













	

	
	








	

















































 




 






 















































 


 




























 























 






















 


 
 




 
 

































 
 





 






















 
 














 








 








 









































 




 






 
#pragma define BRS_19200 13
#pragma define BRK_19200 0
#pragma define BRS_38400 6
#pragma define BRK_38400 8
#pragma define INT_LEVEL_UART 6



 
#pragma define INHNO_SERIAL_IN1 INT_NO_RX0
#pragma define INHNO_SERIAL_OUT1 INT_NO_TX0
#pragma define INHNO_SERIAL_IN2 INT_NO_RX1
#pragma define INHNO_SERIAL_OUT2 INT_NO_TX1





 
typedef struct sio_port_control_block	SIOPCB;



 
#pragma define UART_ERDY_SND 1u
#pragma define UART_ERDY_RCV 2u



 
extern void	uart_initialize(void);



 
extern SIOPCB * uart_opn_por(ID siopid, VP_INT exinf);



 
extern void	uart_cls_por(SIOPCB *siopcb);



 
extern BOOL	uart_snd_chr(SIOPCB *siopcb, char c);



 
extern INT	uart_rcv_chr(SIOPCB *siopcb);



 
extern void	uart_ena_cbr(SIOPCB *siopcb, UINT cbrtn);



 
extern void	uart_dis_cbr(SIOPCB *siopcb, UINT cbrtn);



 
extern void	uart_ierdy_snd(VP_INT exinf);



 
extern void	uart_ierdy_rcv(VP_INT exinf);







 
#pragma define SIO_ERDY_SND UART_ERDY_SND
#pragma define SIO_ERDY_RCV UART_ERDY_RCV





 
#pragma define sio_initialize uart_initialize



 
#pragma define sio_opn_por uart_opn_por



 
#pragma define sio_cls_por uart_cls_por



 
#pragma define sio_snd_chr uart_snd_chr



 
#pragma define sio_rcv_chr uart_rcv_chr



 
#pragma define sio_ena_cbr uart_ena_cbr



 
#pragma define sio_dis_cbr uart_dis_cbr



 
#pragma define sio_ierdy_snd uart_ierdy_snd



 
#pragma define sio_ierdy_rcv uart_ierdy_rcv








































 



 






 

		
		
	



 




 











 













































 



 









































 
















 










 




 




 










  

#pragma define LOGTASK_PRIORITY 3



#pragma define LOGTASK_STACK_SIZE 1024



#pragma define LOGTASK_INTERVAL 10




 
extern void	logtask(VP_INT exinf);




	 

#pragma define TNUM_TSKID 5

const ID _kernel_tmax_tskid = (1 + 5 - 1);

static __STK_UNIT __stack_TASK1[(((128) + sizeof(__STK_UNIT) - 1) / sizeof(__STK_UNIT))];
static __STK_UNIT __stack_TASK2[(((128) + sizeof(__STK_UNIT) - 1) / sizeof(__STK_UNIT))];
static __STK_UNIT __stack_TASK3[(((128) + sizeof(__STK_UNIT) - 1) / sizeof(__STK_UNIT))];
static __STK_UNIT __stack_MAIN_TASK[(((128) + sizeof(__STK_UNIT) - 1) / sizeof(__STK_UNIT))];
static __STK_UNIT __stack_LOGTASK[(((1024) + sizeof(__STK_UNIT) - 1) / sizeof(__STK_UNIT))];

const TINIB _kernel_tinib_table[5] = {
	{0, (VP_INT)(( VP_INT ) 1), (FP)(task), ((UINT)((10) - 1)), (((128) + sizeof(__STK_UNIT) - 1) & ~((SIZE)sizeof(__STK_UNIT) - 1)), __stack_TASK1, 0, (FP)(tex_routine)},
	{0, (VP_INT)(( VP_INT ) 2), (FP)(task), ((UINT)((10) - 1)), (((128) + sizeof(__STK_UNIT) - 1) & ~((SIZE)sizeof(__STK_UNIT) - 1)), __stack_TASK2, 0, (FP)(tex_routine)},
	{0, (VP_INT)(( VP_INT ) 3), (FP)(task), ((UINT)((10) - 1)), (((128) + sizeof(__STK_UNIT) - 1) & ~((SIZE)sizeof(__STK_UNIT) - 1)), __stack_TASK3, 0, (FP)(tex_routine)},
	{0x00u | 0x02u, (VP_INT)(0), (FP)(main_task), ((UINT)((5) - 1)), (((128) + sizeof(__STK_UNIT) - 1) & ~((SIZE)sizeof(__STK_UNIT) - 1)), __stack_MAIN_TASK, 0u, (FP)(((void *)0))},
	{0x00u | 0x02u, (VP_INT)(( VP_INT ) 1), (FP)(logtask), ((UINT)((3) - 1)), (((1024) + sizeof(__STK_UNIT) - 1) & ~((SIZE)sizeof(__STK_UNIT) - 1)), __stack_LOGTASK, 0u, (FP)(((void *)0))}
};

const ID _kernel_torder_table[5] = {1,2,3,4,5};

TCB _kernel_tcb_table[5];


	 

#pragma define TNUM_SEMID 2

const ID _kernel_tmax_semid = (1 + 2 - 1);

const SEMINIB _kernel_seminib_table[2] = {
	{1, 0, 1},
	{1, 1, 1}
};

SEMCB _kernel_semcb_table[2];


	 

#pragma define TNUM_FLGID 0

const ID _kernel_tmax_flgid = (1 + 0 - 1);

const FLGINIB _kernel_flginib_table[];
FLGCB _kernel_flgcb_table[];


	 

#pragma define TNUM_DTQID 0

const ID _kernel_tmax_dtqid = (1 + 0 - 1);

const DTQINIB _kernel_dtqinib_table[];
DTQCB _kernel_dtqcb_table[];


	 

#pragma define TNUM_MBXID 0

const ID _kernel_tmax_mbxid = (1 + 0 - 1);

const MBXINIB _kernel_mbxinib_table[];
MBXCB _kernel_mbxcb_table[];


	 

#pragma define TNUM_MPFID 0

const ID _kernel_tmax_mpfid = (1 + 0 - 1);

const MPFINIB _kernel_mpfinib_table[];
MPFCB _kernel_mpfcb_table[];


	 

#pragma define TNUM_CYCID 1

const ID _kernel_tmax_cycid = (1 + 1 - 1);

const CYCINIB _kernel_cycinib_table[1] = {
	{0,0,(FP)(cyclic_handler),2000,0}
};

CYCCB _kernel_cyccb_table[1];


	 

#pragma define TNUM_INHNO 3

const UINT _kernel_tnum_inhno = 3;

extern void _kernel_interrupt(void); extern void timer_handler(void); void timer_handler_entry(void) { __ASM("	push	xwa	"); __ASM("	push	sr"); __ASM("	pop		wa"); __ASM("	ei		7"); __ASM("	push	xhl	"); __ASM("	ld		xhl, _" "timer_handler" ); __ASM("	jp	__kernel_interrupt" ); };
extern void _kernel_interrupt(void); extern void serial_in_handler1(void); void serial_in_handler1_entry(void) { __ASM("	push	xwa	"); __ASM("	push	sr"); __ASM("	pop		wa"); __ASM("	ei		7"); __ASM("	push	xhl	"); __ASM("	ld		xhl, _" "serial_in_handler1" ); __ASM("	jp	__kernel_interrupt" ); };
extern void _kernel_interrupt(void); extern void serial_out_handler1(void); void serial_out_handler1_entry(void) { __ASM("	push	xwa	"); __ASM("	push	sr"); __ASM("	pop		wa"); __ASM("	ei		7"); __ASM("	push	xhl	"); __ASM("	ld		xhl, _" "serial_out_handler1" ); __ASM("	jp	__kernel_interrupt" ); };

const INHINIB _kernel_inhinib_table[3] = {
	{20,0,(FP)timer_handler_entry},
	{34,0,(FP)serial_in_handler1_entry},
	{35,0,(FP)serial_out_handler1_entry}
};


	 

#pragma define TNUM_EXCNO 1

const UINT _kernel_tnum_excno = 1;

extern void _kernel_interrupt(void); extern void cpuexc_handler(VP p_excinf); void cpuexc_handler_entry(void) { __ASM("	push	xwa	"); __ASM("	push	sr"); __ASM("	pop		wa"); __ASM("	ei		7"); __ASM("	push	xhl	"); __ASM("	ld		xhl, _" "cpuexc_handler" ); __ASM("	jp	__kernel_interrupt" ); };

const EXCINIB _kernel_excinib_table[1] = {
	{3,0,(FP)cpuexc_handler_entry}
};

	 

void
_kernel_call_inirtn(void)
{
	timer_initialize( (VP_INT)(0) );
	serial_initialize( (VP_INT)(0) );
}

void
_kernel_call_terrtn(void)
{
	timer_terminate( (VP_INT)(0) );
}

	 

void
_kernel_object_initialize(void)
{
	_kernel_task_initialize();
	_kernel_semaphore_initialize();
	_kernel_cyclic_initialize();
	_kernel_interrupt_initialize();
	_kernel_exception_initialize();
}

TMEVTN   _kernel_tmevt_heap[5 + 1];