ns9360.h

免费的OS源代码 符合ITRON4.0规范 http://www.toppers.jp/official_release.html

#define	BBUS_GPIO_CONT_STS2_GPIO54		0x00400000				/* GPIO[54] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO55		0x00800000				/* GPIO[55] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO56		0x01000000				/* GPIO[56] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO57		0x02000000				/* GPIO[57] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO58		0x04000000				/* GPIO[58] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO59		0x08000000				/* GPIO[59] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO60		0x10000000				/* GPIO[60] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO61		0x20000000				/* GPIO[61] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO62		0x40000000				/* GPIO[62] control/status bit                     */
#define	BBUS_GPIO_CONT_STS2_GPIO63		0x80000000				/* GPIO[63] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO64		0x00000001				/* GPIO[64] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO65		0x00000002				/* GPIO[65] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO66		0x00000004				/* GPIO[66] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO67		0x00000008				/* GPIO[67] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO68		0x00000010				/* GPIO[68] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO69		0x00000020				/* GPIO[69] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO70		0x00000040				/* GPIO[70] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO71		0x00000080				/* GPIO[71] control/status bit                     */
#define	BBUS_GPIO_CONT_STS3_GPIO72		0x00000100				/* GPIO[72] control/status bit                     */

#define	BBUS_DMA_INT_STS_CH0			0x00000001				/* BBus DMA channel #1 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH1			0x00000002				/* BBus DMA channel #2 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH2			0x00000004				/* BBus DMA channel #3 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH3			0x00000008				/* BBus DMA channel #4 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH4			0x00000010				/* BBus DMA channel #5 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH5			0x00000020				/* BBus DMA channel #6 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH6			0x00000040				/* BBus DMA channel #7 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH7			0x00000080				/* BBus DMA channel #8 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH8			0x00000100				/* BBus DMA channel #9 interrupt status bit        */
#define	BBUS_DMA_INT_STS_CH9			0x00000200				/* BBus DMA channel #10 interrupt status bit       */
#define	BBUS_DMA_INT_STS_CH10			0x00000400				/* BBus DMA channel #11 interrupt status bit       */
#define	BBUS_DMA_INT_STS_CH11			0x00000800				/* BBus DMA channel #12 interrupt status bit       */
#define	BBUS_DMA_INT_STS_CH12			0x00001000				/* BBus DMA channel #13 interrupt status bit       */
#define	BBUS_DMA_INT_STS_CH13			0x00002000				/* BBus DMA channel #14 interrupt status bit       */
#define	BBUS_DMA_INT_STS_CH14			0x00004000				/* BBus DMA channel #14 interrupt status bit       */
#define	BBUS_DMA_INT_STS_CH15			0x00008000				/* BBus DMA channel #15 interrupt status bit       */
#define	BBUS_DMA_INT_STS_CH16			0x00010000				/* BBus DMA channel #16 interrupt status bit       */

#define	BBUS_DMA_INT_ENABLE_CH0			0x00000001				/* BBus DMA channel #1 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH1			0x00000002				/* BBus DMA channel #2 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH2			0x00000004				/* BBus DMA channel #3 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH3			0x00000008				/* BBus DMA channel #4 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH4			0x00000010				/* BBus DMA channel #5 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH5			0x00000020				/* BBus DMA channel #6 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH6			0x00000040				/* BBus DMA channel #7 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH7			0x00000080				/* BBus DMA channel #8 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH8			0x00000100				/* BBus DMA channel #9 interrupt enable bit        */
#define	BBUS_DMA_INT_ENABLE_CH9			0x00000200				/* BBus DMA channel #10 interrupt enable bit       */
#define	BBUS_DMA_INT_ENABLE_CH10		0x00000400				/* BBus DMA channel #11 interrupt enable bit       */
#define	BBUS_DMA_INT_ENABLE_CH11		0x00000800				/* BBus DMA channel #12 interrupt enable bit       */
#define	BBUS_DMA_INT_ENABLE_CH12		0x00001000				/* BBus DMA channel #13 interrupt enable bit       */
#define	BBUS_DMA_INT_ENABLE_CH13		0x00002000				/* BBus DMA channel #14 interrupt enable bit       */
#define	BBUS_DMA_INT_ENABLE_CH14		0x00004000				/* BBus DMA channel #14 interrupt enable bit       */
#define	BBUS_DMA_INT_ENABLE_CH15		0x00008000				/* BBus DMA channel #15 interrupt enable bit       */
#define	BBUS_DMA_INT_ENABLE_CH16		0x00010000				/* BBus DMA channel #16 interrupt enable bit       */


/*
 * Ethernet Control ans Status Registers
 */

/* address */
#define ETH_CONTROL_BASE    0xa0600000			     		 /* Ethernet Control ans Status Registers Base Address */

#define ETH_CONTROL_EGCR1	((UW volatile *) (ETH_CONTROL_BASE + 0x000))
#define ETH_CONTROL_EGCR2	((UW volatile *) (ETH_CONTROL_BASE + 0x004))
#define ETH_CONTROL_EGSR	((UW volatile *) (ETH_CONTROL_BASE + 0x008))
#define ETH_CONTROL_ETSR	((UW volatile *) (ETH_CONTROL_BASE + 0x018))
#define ETH_CONTROL_ERSR	((UW volatile *) (ETH_CONTROL_BASE + 0x01c))
#define ETH_CONTROL_MAC1	((UW volatile *) (ETH_CONTROL_BASE + 0x400))
#define ETH_CONTROL_MAC2	((UW volatile *) (ETH_CONTROL_BASE + 0x404))
#define ETH_CONTROL_IPGT	((UW volatile *) (ETH_CONTROL_BASE + 0x408))
#define ETH_CONTROL_IPGR	((UW volatile *) (ETH_CONTROL_BASE + 0x40c))
#define ETH_CONTROL_CLRT	((UW volatile *) (ETH_CONTROL_BASE + 0x410))
#define ETH_CONTROL_MAXF	((UW volatile *) (ETH_CONTROL_BASE + 0x414))
#define ETH_CONTROL_SUPP	((UW volatile *) (ETH_CONTROL_BASE + 0x418))
#define ETH_CONTROL_MCFG	((UW volatile *) (ETH_CONTROL_BASE + 0x420))
#define ETH_CONTROL_MCMD	((UW volatile *) (ETH_CONTROL_BASE + 0x424))
#define ETH_CONTROL_MADR	((UW volatile *) (ETH_CONTROL_BASE + 0x428))
#define ETH_CONTROL_MWTD	((UW volatile *) (ETH_CONTROL_BASE + 0x42c))
#define ETH_CONTROL_MRDD	((UW volatile *) (ETH_CONTROL_BASE + 0x430))
#define ETH_CONTROL_MIND	((UW volatile *) (ETH_CONTROL_BASE + 0x434))
#define ETH_CONTROL_SA1 	((UW volatile *) (ETH_CONTROL_BASE + 0x440))
#define ETH_CONTROL_SA2 	((UW volatile *) (ETH_CONTROL_BASE + 0x444))
#define ETH_CONTROL_SA3 	((UW volatile *) (ETH_CONTROL_BASE + 0x448))
#define ETH_CONTROL_SAFR	((UW volatile *) (ETH_CONTROL_BASE + 0x500))
#define ETH_CONTROL_HT1 	((UW volatile *) (ETH_CONTROL_BASE + 0x504))
#define ETH_CONTROL_HT2 	((UW volatile *) (ETH_CONTROL_BASE + 0x508))
#define ETH_CONTROL_STAT	((UW volatile *) (ETH_CONTROL_BASE + 0x680))
#define ETH_CONTROL_RXAPTR	((UW volatile *) (ETH_CONTROL_BASE + 0xa00))
#define ETH_CONTROL_RXBPTR	((UW volatile *) (ETH_CONTROL_BASE + 0xa04))
#define ETH_CONTROL_RXCPTR	((UW volatile *) (ETH_CONTROL_BASE + 0xa08))
#define ETH_CONTROL_RXDPTR	((UW volatile *) (ETH_CONTROL_BASE + 0xa0c))
#define ETH_CONTROL_EINTR 	((UW volatile *) (ETH_CONTROL_BASE + 0xa10))
#define ETH_CONTROL_EINTREN	((UW volatile *) (ETH_CONTROL_BASE + 0xa14))
#define ETH_CONTROL_TXPTR 	((UW volatile *) (ETH_CONTROL_BASE + 0xa18))
#define ETH_CONTROL_TXRPTR	((UW volatile *) (ETH_CONTROL_BASE + 0xa1c))
#define ETH_CONTROL_TXERBD	((UW volatile *) (ETH_CONTROL_BASE + 0xa20))
#define ETH_CONTROL_TXSPTR	((UW volatile *) (ETH_CONTROL_BASE + 0xa24))
#define ETH_CONTROL_RXAOFF	((UW volatile *) (ETH_CONTROL_BASE + 0xa28))
#define ETH_CONTROL_RXBOFF	((UW volatile *) (ETH_CONTROL_BASE + 0xa2c))
#define ETH_CONTROL_RXCOFF	((UW volatile *) (ETH_CONTROL_BASE + 0xa30))
#define ETH_CONTROL_RXDOFF	((UW volatile *) (ETH_CONTROL_BASE + 0xa34))
#define ETH_CONTROL_TXOFF 	((UW volatile *) (ETH_CONTROL_BASE + 0xa38))
#define ETH_CONTROL_RXFREE	((UW volatile *) (ETH_CONTROL_BASE + 0xa3c))
#define ETH_CONTROL_TXBD 	((UW volatile *) (ETH_CONTROL_BASE + 0x1000))


/*
 *  充哈みハンドラのベクタ戎规(充哈み庭黎刨)
 */
/*#define INHNO_SIO   INTLV_UART */
#define INHNO_SIO2_RX	57
#define INHNO_SIO2_TX	56
#define INHNO_SIO_RX	59
#define INHNO_SIO_TX	58
#define	INHNO_BBB		8
#define	INHNO_ETH_RX	5
#define	INHNO_ETH_TX	6
#define	INHNO_ETH_LINK	7
#define	INHNO_USB_HOST_D	25
#define	INHNO_USBDEV	26

#ifndef _MACRO_ONLY

/*
 * カ〖ネル弹瓢箕脱の介袋步(sys_putcを蝗脱するため)
 */
extern void uart_init(ID siopid);

/*
 *  シリアルI/Oポ〖ト介袋步ブロック
 */
typedef struct sio_port_initialization_block {
	
	VP		pSraReg;           /* SRA Reg Address                 */
	VP		pFifoReg;          /* FIFO Reg Address                */
	VP		pCraReg;           /* CRA Reg Address                 */
	VP		pCrbReg;           /* CRB Reg Address                 */
	VP		pRctReg;           /* RCT Reg Address                 */
	VP		pRbtReg;           /* RBT Reg Address                 */
	VP		pBrgReg;           /* BRG Reg Address                 */
	UW		CraData;           /* CRA Reg Set Data                */
	UW		CrbData;           /* CRB Reg Set Data                */
	UW		RctData;           /* RCT Reg Set Data                */
	UW		RbtData;           /* RBT Reg Set Data                */
	UW		BrgData;           /* BRG Reg Set Data                */
	UW		BbbiTx;            /* BBUS Bridge TX INT Control      */
	UW		BbbiRx;            /* BBUS Bridge RX INT Control      */

} SIOPINIB;

/*
 *  シリアルI/Oポ〖ト瓷妄ブロックの年盗
 */
typedef struct sio_port_control_block {
    const SIOPINIB  *siopinib; /* シリアルI/Oポ〖ト介袋步ブロック */
    VP_INT          exinf;     /* 橙磨攫鼠 */
    BOOL    openflag;          /* オ〖プン貉みフラグ */
    BOOL    sendflag;          /* 流慨充哈みイネ〖ブルフラグ */
    BOOL    getready;          /* 矢机を减慨した觉轮 */
    BOOL    putready;          /* 矢机を流慨できる觉轮 */
    UW		rxfdb;             /* rxbuf柒の减慨バイト眶 */
    UW		rxbuf;             /* 减慨バッファ */
	ID		siopid;
}SIOPCB;

/*
 *  コ〖ルバックル〖チンの急侍戎规
 */
#define SIO_ERDY_SND    1u      /* 流慨材墙コ〖ルバック */
#define SIO_ERDY_RCV    2u      /* 减慨奶梦コ〖ルバック */


/*
 *  オンチップのUARTからのポ〖リング叫蜗
 */
extern void uart_putc(char c);

/*
 *  SIOドライバの介袋步ル〖チン
 */
extern void uart_initialize(void);


/*
 *  オ〖プンしているポ〖ト