ns9360.h

免费的OS源代码 符合ITRON4.0规范 http://www.toppers.jp/official_release.html

#define	SC1BRG_REG		0x9020004C		/* Channel A Bit-Rate register */
#define	SC1FIFO_REG		0x90200050		/* Channel A FIFO Data register */
#define	SC1RBT_REG		0x90200054		/* Channel A Receive Buffer Gap Timer */
#define	SC1RCT_REG		0x90200058		/* Channel A Receive Character Gap Timer */
#define	SC1RMR_REG		0x9020005C		/* Channel A Receive Match register */
#define	SC1RMM_REG		0x90200060		/* Channel A Receive Match Mask register */
#define	SC1FCR_REG		0x90200074		/* Channel A Flow Control register */
#define	SC1FCF_REG		0x90200078		/* Channel A Flow Control Force register */

#define	SC3CRA_REG		0x90300000		/* Channel C Control Register A */
#define	SC3CRB_REG		0x90300004		/* Channel C Control Register B */
#define	SC3SRA_REG		0x90300008		/* Channel C Status Register A */
#define	SC3BRG_REG		0x9030000C		/* Channel C Bit-Rate register */
#define	SC3FIFO_REG		0x90300010		/* Channel C FIFO Data register */
#define	SC3RBT_REG		0x90300014		/* Channel C Receive Buffer Gap Timer */
#define	SC3RCT_REG		0x90300018		/* Channel C Receive Character Gap Timer */
#define	SC3RMR_REG		0x9030001C		/* Channel C Receive Match register */
#define	SC3RMM_REG		0x90300020		/* Channel C Receive Match Mask register */
#define	SC3FCR_REG		0x90300034		/* Channel C Flow Control register */
#define	SC3FCF_REG		0x90300038		/* Channel C Flow Control Force register */

#define	SC4CRA_REG		0x90300040		/* Channel D Control Register A */
#define	SC4CRB_REG		0x90300044		/* Channel D Control Register B */
#define	SC4SRA_REG		0x90300048		/* Channel D Status Register A */
#define	SC4BRG_REG		0x9030004C		/* Channel D Bit-Rate register */
#define	SC4FIFO_REG		0x90300050		/* Channel D FIFO Data register */
#define	SC4RBT_REG		0x90300054		/* Channel D Receive Buffer Gap Timer */
#define	SC4RCT_REG		0x90300058		/* Channel D Receive Character Gap Timer */
#define	SC4RMR_REG		0x9030005C		/* Channel D Receive Match register */
#define	SC4RMM_REG		0x90300060		/* Channel D Receive Match Mask register */
#define	SC4FCR_REG		0x90300074		/* Channel D Flow Control register */
#define	SC4FCF_REG		0x90300078		/* Channel D Flow Control Force register */

/* Serial Channel Control Register bit define */
#define	SCCRA_CE		0x80000000		/* 1... .... .... .... .... .... .... .... */
#define	SCCRA_BRK		0x40000000		/* .1.. .... .... .... .... .... .... .... */
#define	SCCRA_STICK		0x20000000		/* ..1. .... .... .... .... .... .... .... */
#define	SCCRA_EPS		0x10000000		/* ...1 .... .... .... .... .... .... .... */
#define	SCCRA_PE		0x08000000		/* .... 1... .... .... .... .... .... .... */
#define	SCCRA_STOP		0x04000000		/* .... .1.. .... .... .... .... .... .... */
#define	SCCRA_WLS		0x03000000		/* .... ..11 .... .... .... .... .... .... */
#define	SCCRA_CTSTX		0x00800000		/* .... .... 1... .... .... .... .... .... */
#define	SCCRA_RTSRX		0x00400000		/* .... .... .1.. .... .... .... .... .... */
#define	SCCRA_RL		0x00200000		/* .... .... ..1. .... .... .... .... .... */
#define	SCCRA_LL		0x00100000		/* .... .... ...1 .... .... .... .... .... */
#define	SCCRA_DTR		0x00020000		/* .... .... .... ..1. .... .... .... .... */
#define	SCCRA_RTS		0x00010000		/* .... .... .... ...1 .... .... .... .... */
#define	SCCRA_RIE		0x00000e00		/* .... .... .... .... .... 111. .... .... */
#define	SCCRA_ERXDMA	0x00000100		/* .... .... .... .... .... ...1 .... .... */
#define	SCCRA_RIC		0x000000e0		/* .... .... .... .... .... .... 111. .... */
#define	SCCRA_TIC		0x0000001e		/* .... .... .... .... .... .... ...1 111. */
#define	SCCRA_ETXDMA	0x00000001		/* .... .... .... .... .... .... .... ...1 */
#define	SCCRB_RDM		0xf0000000		/* 1111 .... .... .... .... .... .... .... */
#define	SCCRB_RBGT		0x08000000		/* .... 1... .... .... .... .... .... .... */
#define	SCCRB_RCGT		0x04000000		/* .... .1.. .... .... .... .... .... .... */
#define	SCCRB_MODE		0x00300000		/* .... .... ..11 .... .... .... .... .... */
#define	SCCRB_BITORDR	0x00080000		/* .... .... .... 1... .... .... .... .... */
#define	SCCRB_RTSTX		0x00008000		/* .... .... .... .... 1... .... .... .... */

/* Serial Channel Status Register bit define */
#define	SCSRA_MATCH		0xf0000000		/* 1111 .... .... .... .... .... .... .... */
#define	SCSRA_BGAP		0x08000000		/* .... 1... .... .... .... .... .... .... */
#define	SCSRA_CGAP		0x04000000		/* .... .1.. .... .... .... .... .... .... */
#define	SCSRA_RXFDB		0x00300000		/* .... .... ..11 .... .... .... .... .... */
#define	SCSRA_DCD		0x00080000		/* .... .... .... 1... .... .... .... .... */
#define	SCSRA_RI		0x00040000		/* .... .... .... .1.. .... .... .... .... */
#define	SCSRA_DSR		0x00020000		/* .... .... .... ..1. .... .... .... .... */
#define	SCSRA_CTS		0x00010000		/* .... .... .... ...1 .... .... .... .... */
#define	SCSRA_RBRK		0x00008000		/* .... .... .... .... 1... .... .... .... */
#define	SCSRA_RFE		0x00004000		/* .... .... .... .... .1.. .... .... .... */
#define	SCSRA_RPE		0x00002000		/* .... .... .... .... ..1. .... .... .... */
#define	SCSRA_ROVER		0x00001000		/* .... .... .... .... ...1 .... .... .... */
#define	SCSRA_RRDY		0x00000800		/* .... .... .... .... .... 1... .... .... */
#define	SCSRA_RHALF		0x00000400		/* .... .... .... .... .... .1.. .... .... */
#define	SCSRA_RBC		0x00000200		/* .... .... .... .... .... ..1. .... .... */
#define	SCSRA_RFS		0x00000100		/* .... .... .... .... .... ...1 .... .... */
#define	SCSRA_DCDI		0x00000080		/* .... .... .... .... .... .... 1... .... */
#define	SCSRA_RII		0x00000040		/* .... .... .... .... .... .... .1.. .... */
#define	SCSRA_DSRI		0x00000020		/* .... .... .... .... .... .... ..1. .... */
#define	SCSRA_CTSI		0x00000010		/* .... .... .... .... .... .... ...1 .... */
#define	SCSRA_TRDY		0x00000008		/* .... .... .... .... .... .... .... 1... */
#define	SCSRA_THALF		0x00000004		/* .... .... .... .... .... .... .... .1.. */
#define	SCSRA_TEMPTY	0x00000001		/* .... .... .... .... .... .... .... ...1 */


/*
 *Memory Controller Registers
 */
#define MEM_CONTROLLER_BASE      0xA0700000 /* ARM MPMC Memory Controller Registers  Base Address */
#define HIGHEST_HW     0xFFFEFFF0 /* Highest *hardware only* address, use for termination */
#define CS_BASE_SHIFT_BITS                      12
#define CS_MASK_SHIFT_BITS                      12


#define MPMCControl_REG            ((UW volatile *) (MEM_CONTROLLER_BASE + 0x0))
#define MPMCStatus_REG             ((UW volatile *) (MEM_CONTROLLER_BASE + 0x4))
#define MPMCConfig_REG             ((UW volatile *) (MEM_CONTROLLER_BASE + 0x8))
#define MPMCDynamicControl_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x20))    
#define MPMCDynamicRefresh_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x24))
#define MPMCDynamicReadConfig_REG  ((UW volatile *) (MEM_CONTROLLER_BASE + 0x28))
#define MPMCDynamictRP_REG         ((UW volatile *) (MEM_CONTROLLER_BASE + 0x30))
#define MPMCDynamictRAS_REG        ((UW volatile *) (MEM_CONTROLLER_BASE + 0x34))
#define MPMCDynamictSREX_REG       ((UW volatile *) (MEM_CONTROLLER_BASE + 0x38))
#define MPMCDynamictAPR_REG        ((UW volatile *) (MEM_CONTROLLER_BASE + 0x3C))
#define MPMCDynamictDAL_REG        ((UW volatile *) (MEM_CONTROLLER_BASE + 0x40))
#define MPMCDynamictWR_REG         ((UW volatile *) (MEM_CONTROLLER_BASE + 0x44))
#define MPMCDynamictRC_REG         ((UW volatile *) (MEM_CONTROLLER_BASE + 0x48))
#define MPMCDynamictRFC_REG        ((UW volatile *) (MEM_CONTROLLER_BASE + 0x4C))
#define MPMCDynamictXSR_REG        ((UW volatile *) (MEM_CONTROLLER_BASE + 0x50))
#define MPMCDynamictRRD_REG        ((UW volatile *) (MEM_CONTROLLER_BASE + 0x54))
#define MPMCDynamictMRD_REG        ((UW volatile *) (MEM_CONTROLLER_BASE + 0x58))
#define MPMCStaticExtendedWait_REG ((UW volatile *) (MEM_CONTROLLER_BASE + 0x80))
#define MPMCDynamicConfig0_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x100))
#define MPMCDynamicRasCas0_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x104))
#define MPMCDynamicConfig1_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x120))
#define MPMCDynamicRasCas1_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x124))
#define MPMCDynamicConfig2_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x140))
#define MPMCDynamicRasCas2_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x144))
#define MPMCDynamicConfig3_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x160))
#define MPMCDynamicRasCas3_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x164))
#define MPMCStaticConfig0_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x200))
#define MPMCStaticWaitWen0_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x204))
#define MPMCStaticWaitOen0_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x208))
#define MPMCStaticWaitRd0_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x20C))
#define MPMCStaticWaitPage0_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x210))
#define MPMCStaticWaitWr0_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x214))
#define MPMCStaticWaitTurn0_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x218))
#define MPMCStaticConfig1_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x220))
#define MPMCStaticWaitWen1_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x224))
#define MPMCStaticWaitOen1_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x228))
#define MPMCStaticWaitRd1_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x22C))
#define MPMCStaticWaitPage1_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x230))
#define MPMCStaticWaitWr1_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x234))
#define MPMCStaticWaitTurn1_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x238))
#define MPMCStaticConfig2_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x240))
#define MPMCStaticWaitWen2_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x244))
#define MPMCStaticWaitOen2_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x248))
#define MPMCStaticWaitRd2_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x24C))
#define MPMCStaticWaitPage2_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x250))
#define MPMCStaticWaitWr2_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x254))
#define MPMCStaticWaitTurn2_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x258))
#define MPMCStaticConfig3_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x260))
#define MPMCStaticWaitWen3_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x264))
#define MPMCStaticWaitOen3_REG    ((UW volatile *) (MEM_CONTROLLER_BASE + 0x268))
#define MPMCStaticWaitRd3_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x26C))
#define MPMCStaticWaitPage3_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x270))
#define MPMCStaticWaitWr3_REG     ((UW volatile *) (MEM_CONTROLLER_BASE + 0x274))
#define MPMCStaticWaitTurn3_REG   ((UW volatile *) (MEM_CONTROLLER_BASE + 0x278))


/* PrimeCell MultiPort Memory Controller defines */
    #define MPMC_DYNAMIC_REFRESH_refresh 10, 0
    #define MPMC_DYNAMIC_CONFIG0_config    31, 0
    #define MPMC_DYNAMIC_RASCAS0_rascas    31, 0
    #define MPMC_DYNAMIC_CONFIG1_config   31, 0
    #define MPMC_DYNAMIC_RASCAS1_rascas    31, 0
    #define MPMC_DYNAMIC_CONFIG2_config  31, 0
    #define MPMC_DYNAMIC_RASCAS2_rascas  31, 0
    #define MPMC_DYNAMIC_CONFIG3_config   31, 0
    #define MPMC_DYNAMIC_RASCAS3_rascas   31, 0

    /* Defines for static memory */
    #define MPMC_STATIC_CONFIG0_config     0x82
    #define MPMC_STATIC_WAIT_WEN0_wen      0x02
    #define MPMC_STATIC_WAIT_OEN0_oen      0x02
    #define MPMC_STATIC_WAIT_RD0_rd        0x09
    #define MPMC_STATIC_WAIT_PAGE0_page    0x02
    #define MPMC_STATIC_WAIT_WR0_wr        0x09
    #define MPMC_STATIC_WAIT_TURN0_turn    0x02

    #define MPMC_STATIC_CONFIG1_config     0x81
    #define MPMC_STATIC_WAIT_WEN1_wen      0x00
    #define MPMC_STATIC_WAIT_OEN1_oen      0x00
    #define MPMC_STATIC_WAIT_RD1_rd        0x08
    #define MPMC_STATIC_WAIT_PAGE1_page    0x00
    #define MPMC_STATIC_WAIT_WR1_wr        0x04
    #define MPMC_STATIC_WAIT_TURN1_turn    0x00

    #define MPMC_STATIC_CONFIG2_config     0x82
    #define MPMC_STATIC_WAIT_WEN2_wen      0x02
    #define MPMC_STATIC_WAIT_OEN2_oen      0x02
    #define MPMC_STATIC_WAIT_RD2_rd        0x09
    #define MPMC_STATIC_WAIT_PAGE2_page    0x02
    #define MPMC_STATIC_WAIT_WR2_wr        0x09
    #define MPMC_STATIC_WAIT_TURN2_turn    0x02

    #define MPMC_STATIC_CONFIG3_config     0x82
    #define MPMC_STATIC_WAIT_WEN3_wen      0x02
    #define MPMC_STATIC_WAIT_OEN3_oen      0x02
    #define MPMC_STATIC_WAIT_RD3_rd        0x09