ns9360.h

免费的OS源代码 符合ITRON4.0规范 http://www.toppers.jp/official_release.html

#define	BBBI_S2RX			0x00000004
#define	BBBI_USB			0x00000002
#define	BBBI_DMA			0x00000001

#define	BBBIS_MASK			0x03000fff;							/* BBus Interrupt Status register Mask patern */


/*
 * Chip Select Registers
 */
#define	CS4B_REG			(SYS_CONT_MODULE_BASE+0x01D0)		/* System Memory Chip Select 4 Dynamic Memory Base					*/
#define	CS4M_REG			(SYS_CONT_MODULE_BASE+0x01D4)		/* System Memory Chip Select 4 Dynamic Memory Mask					*/
#define	CS5B_REG			(SYS_CONT_MODULE_BASE+0x01D8)		/* System Memory Chip Select 5 Dynamic Memory Base					*/
#define	CS5M_REG			(SYS_CONT_MODULE_BASE+0x01DC)		/* System Memory Chip Select 5 Dynamic Memory Mask					*/
#define	CS6B_REG			(SYS_CONT_MODULE_BASE+0x01E0)		/* System Memory Chip Select 6 Dynamic Memory Base					*/
#define	CS6M_REG			(SYS_CONT_MODULE_BASE+0x01E4)		/* System Memory Chip Select 6 Dynamic Memory Mask					*/
#define	CD7B_REG			(SYS_CONT_MODULE_BASE+0x01E8)		/* System Memory Chip Select 7 Dynamic Memory Base					*/
#define	CS7M_REG			(SYS_CONT_MODULE_BASE+0x01EC)		/* System Memory Chip Select 7 Dynamic Memory Mask					*/
#define	CS0B_REG			(SYS_CONT_MODULE_BASE+0x01F0)		/* System Memory Chip Select 0 Static Memory Base					*/
#define	CS0M_REG			(SYS_CONT_MODULE_BASE+0x01F4)		/* System Memory Chip Select 0 Static Memory Mask					*/
#define	CS1B_REG			(SYS_CONT_MODULE_BASE+0x01F8)		/* System Memory Chip Select 1 Static Memory Base					*/
#define	CS1M_REG			(SYS_CONT_MODULE_BASE+0x01FC)		/* System Memory Chip Select 1 Static Memory Mask					*/
#define	CS2B_REG			(SYS_CONT_MODULE_BASE+0x0200)		/* System Memory Chip Select 2 Static Memory Base					*/
#define	CS2M_REG			(SYS_CONT_MODULE_BASE+0x0204)		/* System Memory Chip Select 2 Static Memory Mask					*/
#define	CS3B_REG			(SYS_CONT_MODULE_BASE+0x0208)		/* System Memory Chip Select 3 Static Memory Base					*/
#define	CS3M_REG			(SYS_CONT_MODULE_BASE+0x020C)		/* System Memory Chip Select 3 Static Memory Mask					*/

/*
 *Timer Registers
 */
#define	TIMER0_RLC_REG		(SYS_CONT_MODULE_BASE+0x0044)		/* Timer 0 Reload Count register									*/
#define	TIMER1_RLC_REG		(SYS_CONT_MODULE_BASE+0x0048)		/* Timer 1 Reload Count register									*/
#define	TIMER2_RLC_REG		(SYS_CONT_MODULE_BASE+0x004C)		/* Timer 2 Reload Count register									*/
#define	TIMER3_RLC_REG		(SYS_CONT_MODULE_BASE+0x0050)		/* Timer 3 Reload Count register									*/
#define	TIMER4_RLC_REG		(SYS_CONT_MODULE_BASE+0x0054)		/* Timer 4 Reload Count register									*/
#define	TIMER5_RLC_REG		(SYS_CONT_MODULE_BASE+0x0058)		/* Timer 5 Reload Count register									*/
#define	TIMER6_RLC_REG		(SYS_CONT_MODULE_BASE+0x005C)		/* Timer 6 Reload Count register									*/
#define	TIMER7_RLC_REG		(SYS_CONT_MODULE_BASE+0x0060)		/* Timer 7 Reload Count register									*/
#define	TIMER8_RLC_REG		(SYS_CONT_MODULE_BASE+0x0064)		/* Timer 8 Reload Count register									*/
#define	TIMER9_RLC_REG		(SYS_CONT_MODULE_BASE+0x0068)		/* Timer 9 Reload Count register									*/
#define	TIMER10_RLC_REG		(SYS_CONT_MODULE_BASE+0x006C)		/* Timer 10 Reload Count register									*/
#define	TIMER11_RLC_REG		(SYS_CONT_MODULE_BASE+0x0070)		/* Timer 11 Reload Count register									*/
#define	TIMER12_RLC_REG		(SYS_CONT_MODULE_BASE+0x0074)		/* Timer 12 Reload Count register									*/
#define	TIMER13_RLC_REG		(SYS_CONT_MODULE_BASE+0x0078)		/* Timer 13 Reload Count register									*/
#define	TIMER14_RLC_REG		(SYS_CONT_MODULE_BASE+0x007C)		/* Timer 14 Reload Count register									*/
#define	TIMER15_RLC_REG		(SYS_CONT_MODULE_BASE+0x0080)		/* Timer 15 Reload Count register									*/
#define	TIMER0_RR			(SYS_CONT_MODULE_BASE+0x0084)		/* Timer 0 Read register											*/
#define	TIMER1_RR			(SYS_CONT_MODULE_BASE+0x0088)		/* Timer 1 Read register											*/
#define	TIMER2_RR			(SYS_CONT_MODULE_BASE+0x008C)		/* Timer 2 Read register											*/
#define	TIMER3_RR			(SYS_CONT_MODULE_BASE+0x0090)		/* Timer 3 Read register											*/
#define	TIMER4_RR			(SYS_CONT_MODULE_BASE+0x0094)		/* Timer 4 Read register											*/
#define	TIMER5_RR			(SYS_CONT_MODULE_BASE+0x0098)		/* Timer 5 Read register											*/
#define	TIMER6_RR			(SYS_CONT_MODULE_BASE+0x009C)		/* Timer 6 Read register											*/
#define	TIMER7_RR			(SYS_CONT_MODULE_BASE+0x00A0)		/* Timer 7 Read register											*/
#define	TIMER8_RR			(SYS_CONT_MODULE_BASE+0x00A4)		/* Timer 8 Read register											*/
#define	TIMER9_RR			(SYS_CONT_MODULE_BASE+0x00A8)		/* Timer 9 Read register											*/
#define	TIMER10_RR			(SYS_CONT_MODULE_BASE+0x00AC)		/* Timer 10 Read register											*/
#define	TIMER11_RR			(SYS_CONT_MODULE_BASE+0x00B0)		/* Timer 11 Read register											*/
#define	TIMER12_RR			(SYS_CONT_MODULE_BASE+0x00B4)		/* Timer 12 Read register											*/
#define	TIMER13_RR			(SYS_CONT_MODULE_BASE+0x00B8)		/* Timer 13 Read register											*/
#define	TIMER14_RR			(SYS_CONT_MODULE_BASE+0x00BC)		/* Timer 14 Read register											*/
#define	TIMER15_RR			(SYS_CONT_MODULE_BASE+0x00C0)		/* Timer 15 Read register											*/
#define	TIS_REG				(SYS_CONT_MODULE_BASE+0x0170)		/* Timer Interrupt Status register									*/
#define	TIMER0_CR			(SYS_CONT_MODULE_BASE+0x0190)		/* Timer 0 Control register											*/
#define	TIMER1_CR			(SYS_CONT_MODULE_BASE+0x0194)		/* Timer 1 Control register											*/
#define	TIMER2_CR			(SYS_CONT_MODULE_BASE+0x0198)		/* Timer 2 Control register											*/
#define	TIMER3_CR			(SYS_CONT_MODULE_BASE+0x019C)		/* Timer 3 Control register											*/
#define	TIMER4_CR			(SYS_CONT_MODULE_BASE+0x01A0)		/* Timer 4 Control register											*/
#define	TIMER5_CR			(SYS_CONT_MODULE_BASE+0x01A4)		/* Timer 5 Control register											*/
#define	TIMER6_CR			(SYS_CONT_MODULE_BASE+0x01A8)		/* Timer 6 Control register											*/
#define	TIMER7_CR			(SYS_CONT_MODULE_BASE+0x01AC)		/* Timer 7 Control register											*/
#define	TIMER8_CR			(SYS_CONT_MODULE_BASE+0x01B0)		/* Timer 8 Control register											*/
#define	TIMER9_CR			(SYS_CONT_MODULE_BASE+0x01B4)		/* Timer 9 Control register											*/
#define	TIMER10_CR			(SYS_CONT_MODULE_BASE+0x01B8)		/* Timer 10 Control register										*/
#define	TIMER11_CR			(SYS_CONT_MODULE_BASE+0x01BC)		/* Timer 11 Control register										*/
#define	TIMER12_CR			(SYS_CONT_MODULE_BASE+0x01C0)		/* Timer 12 Control register										*/
#define	TIMER13_CR			(SYS_CONT_MODULE_BASE+0x01C4)		/* Timer 13 Control register										*/
#define	TIMER14_CR			(SYS_CONT_MODULE_BASE+0x01C8)		/* Timer 14 Control register										*/
#define	TIMER15_CR			(SYS_CONT_MODULE_BASE+0x01CC)		/* Timer 15 Control register										*/

/* Defines for the SCM modules dynamic (RAM) chip selects */
#define SCM_CS4_BASE_REG	(SYS_CONT_MODULE_BASE+0x01D0)
#define SCM_CS4_MASK_REG	(SYS_CONT_MODULE_BASE+0x01D4)
#define SCM_CS5_BASE_REG	(SYS_CONT_MODULE_BASE+0x01D8)
#define SCM_CS5_MASK_REG	(SYS_CONT_MODULE_BASE+0x01DC)
#define SCM_CS6_BASE_REG	(SYS_CONT_MODULE_BASE+0x01E0)
#define SCM_CS6_MASK_REG	(SYS_CONT_MODULE_BASE+0x01E4)
#define SCM_CS7_BASE_REG	(SYS_CONT_MODULE_BASE+0x01E8)
#define SCM_CS7_MASK_REG	(SYS_CONT_MODULE_BASE+0x01EC)

/* Defines for the SCM modules static chip selects */
#define SCM_CS0_BASE_REG	(SYS_CONT_MODULE_BASE+0x01F0)
#define SCM_CS0_MASK_REG	(SYS_CONT_MODULE_BASE+0x01F4)
#define SCM_CS1_BASE_REG	(SYS_CONT_MODULE_BASE+0x01F8)
#define SCM_CS1_MASK_REG	(SYS_CONT_MODULE_BASE+0x01FC)
#define SCM_CS2_BASE_REG	(SYS_CONT_MODULE_BASE+0x0200)
#define SCM_CS2_MASK_REG	(SYS_CONT_MODULE_BASE+0x0204)
#define SCM_CS3_BASE_REG	(SYS_CONT_MODULE_BASE+0x0208)
#define SCM_CS3_MASK_REG	(SYS_CONT_MODULE_BASE+0x020C)

/*
 *Interrupt ID
 */
#define	INT_ID_WDT			0									/* WDT Interrupt ID													*/
#define	INT_ID_AHB_ER		1									/* AHB Bus Error Interrupt ID										*/
#define	INT_ID_BBUS_INT		2									/* BBus Aggregate Interrupt ID										*/
#define	INT_ID_ETH_RX		4									/* Ethernet Module Receive Interrupt ID								*/
#define	INT_ID_ETH_TX		5									/* Ethernet Module Transmit Interrupt ID							*/
#define	INT_ID_ETH_PHY		6									/* Ethernet Phy Interrupt ID										*/
#define	INT_ID_LCD			7									/* LCD Module interrupt ID											*/
#define	INT_ID_PCI_BRG		8									/* PCI Bridge Module Interrupt ID									*/
#define	INT_ID_PCI_ABT		9									/* PCI Arbiter Module Interrupt ID									*/
#define	INT_ID_PCI_EX0		10									/* PCI External Interrupt 0 ID										*/
#define	INT_ID_PCI_EX1		11									/* PCI External Interrupt 1 ID										*/
#define	INT_ID_PCI_EX2		12									/* PCI External Interrupt 2 ID										*/
#define	INT_ID_PCI_EX3		13									/* PCI External Interrupt 3 ID										*/
#define	INT_ID_I2C			14									/* I2C Interrupt ID													*/
#define	INT_ID_BBUS_DMA		15									/* BBus DMA Interrupt ID											*/
#define	INT_ID_TIMER0		16									/* Timer Interrupt 0 ID												*/
#define	INT_ID_TIMER1		17									/* Timer Interrupt 1 ID												*/
#define	INT_ID_TIMER2		18									/* Timer Interrupt 2 ID												*/
#define	INT_ID_TIMER3		19									/* Timer Interrupt 3 ID												*/
#define	INT_ID_TIMER4		20									/* Timer Interrupt 4 ID												*/
#define	INT_ID_TIMER5		21									/* Timer Interrupt 5 ID												*/
#define	INT_ID_TIMER6		22									/* Timer Interrupt 6 ID												*/
#define	INT_ID_TIMER7		23									/* Timer Interrupt 7 ID												*/
#define	INT_ID_TIMER89		24									/* Timer Interrupt 8 and 9 ID										*/
#define	INT_ID_USB_HOST		25									/* USB HOST Interrupt ID											*/
#define	INT_ID_USB_DEV		26									/* USB DEVIDE Interrupt ID											*/
#define	INT_ID_TIMER1415	27									/* Timer Interrupt 14 and 15 ID										*/
#define	INT_ID_EXT_INT0		28									/* External Interrupt 0 ID											*/
#define	INT_ID_EXT_INT1		29									/* External Interrupt 1 ID											*/
#define	INT_ID_EXT_INT2		30									/* External Interrupt 2 ID											*/
#define	INT_ID_EXT_INT3		31									/* External Interrupt 3 ID											*/
/* これ笆惯はBBusの充哈みID */          
#define	INT_ID_BBUS_F		32									/* BBus Interrupt First ID											*/
#define	INT_ID_BBUS_RFU30	33									/* BBus Interrupt RFU (bit30)										*/
#define	INT_ID_BBUS_RFU29	34									/* BBus Interrupt RFU (bit29)										*/
#define	INT_ID_BBUS_RFU28	35									/* BBus Interrupt RFU (bit28)										*/
#define	INT_ID_BBUS_RFU27	36									/* BBus Interrupt RFU (bit27)										*/
#define	INT_ID_BBUS_RFU26	37									/* BBus Interrupt RFU (bit26)										*/
#define	INT_ID_AHB_DMA2		38									/* AHB_DMA2 Interrupt (BBus bit25)									*/
#define	INT_ID_AHB_DMA1		39									/* AHB_DMA1 Interrupt (BBus bit24)									*/
#define	INT_ID_BBUS_RFU23	40									/* BBus Interrupt RFU (bit23)										*/
#define	INT_ID_BBUS_RFU22	41									/* BBus Interrupt RFU (bit22)										*/
#define	INT_ID_BBUS_RFU21	42									/* BBus Interrupt RFU (bit21)										*/
#define	INT_ID_BBUS_RFU20	43									/* BBus Interrupt RFU (bit20)										*/
#define	INT_ID_BBUS_RFU19	44									/* BBus Interrupt RFU (bit19)										*/
#define	INT_ID_BBUS_RFU18	45									/* BBus Interrupt RFU (bit18)										*/
#define	INT_ID_BBUS_RFU17	46									/* BBus Interrupt RFU (bit17)										*/
#define	INT_ID_BBUS_RFU16	47									/* BBus Interrupt RFU (bit16)										*/
#define	INT_ID_BBUS_RFU15	48									/* BBus Interrupt RFU (bit15)										*/
#define	INT_ID_BBUS_RFU14	49									/* BBus Interrupt RFU (bit14)										*/
#define	INT_ID_BBUS_RFU13	50									/* BBus Interrupt RFU (bit13)										*/
#define	INT_ID_BBUS_RFU12	51									/* BBus Interrupt RFU (bit12)										*/
#define	INT_ID_1284			52									/* IEEE 1284 Module Interrupt (BBus bit11)							*/
#define	INT_ID_BI2C			53									/* I2C Interrupt (BBus bit10)										*/
#define	INT_ID_SERD_TX		54									/* SER D Tx Interrupt (BBus bit9)									*/
#define	INT_ID_SERD_RX		55									/* SER D Rx Interrupt (BBus bit8)									*/
#define	INT_ID_SERC_TX		56									/* SER C Tx Interrupt (BBus bit7)									*/
#define	INT_ID_SERC_RX		57									/* SER C Rx Interrupt (BBus bit6)									*/
#define	INT_ID_SERA_TX		58									/* SER A Tx Interrupt (BBus bit5)									*/
#define	INT_ID_SERA_RX		59									/* SER A Rx Interrupt (BBus bit4)									*/
#define	INT_ID_SERB_TX		60									/* SER B Tx Interrupt (BBus bit3)									*/
#define	INT_ID_SERB_RX		61									/* SER B Rx Interrupt (BBus bit2)									*/
#define	INT_ID_USB			62									/* USB module Interrupt (BBus bit1)									*/
#define	INT_ID_DMAE			63									/* BBus DMA aggregate Interrupt (BBus bit0)							*/

#define	INT_ID_NONE			0xff								/* unuse ID */
#define	BBUS_IRQ_NUM		32									/* BBus IRQ start number											*/


/*
 * Serial Controller Registers
 */
#define	SC2CRA_REG		0x90200000		/* Channel B Control Register A */
#define	SC2CRB_REG		0x90200004		/* Channel B Control Register B */
#define	SC2SRA_REG		0x90200008		/* Channel B Status Register A */
#define	SC2BRG_REG		0x9020000C		/* Channel B Bit-Rate register */
#define	SC2FIFO_REG		0x90200010		/* Channel B FIFO Data register */
#define	SC2RBT_REG		0x90200014		/* Channel B Receive Buffer Gap Timer */
#define	SC2RCT_REG		0x90200018		/* Channel B Receive Character Gap Timer */
#define	SC2RMR_REG		0x9020001C		/* Channel B Receive Match register */
#define	SC2RMM_REG		0x90200020		/* Channel B Receive Match Mask register */
#define	SC2FCR_REG		0x90200034		/* Channel B Flow Control register */
#define	SC2FCF_REG		0x90200038		/* Channel B Flow Control Force register */

#define	SC1CRA_REG		0x90200040		/* Channel A Control Register A */
#define	SC1CRB_REG		0x90200044		/* Channel A Control Register B */
#define	SC1SRA_REG		0x90200048		/* Channel A Status Register A */