sinewave.fit.qmsg

sinewave程序是一个正弦波发生器程序。256点查表法

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal Global clock " "Info: Automatically promoted signal \"sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal\" to use Global clock" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 36 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29 Global clock " "Info: Automatically promoted signal \"sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29\" to use Global clock" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.414 ns register register " "Info: Estimated most critical path is register to register delay of 3.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 1 REG LAB_X31_Y14 60 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y14; Fanout = 60; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.522 ns) 0.898 ns sld_hub:sld_hub_inst\|hub_tdo~275 2 COMB LAB_X32_Y14 1 " "Info: 2: + IC(0.376 ns) + CELL(0.522 ns) = 0.898 ns; Loc. = LAB_X32_Y14; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~275'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "0.898 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~275 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.101 ns) 2.093 ns sld_hub:sld_hub_inst\|hub_tdo~278 3 COMB LAB_X30_Y14 1 " "Info: 3: + IC(1.094 ns) + CELL(0.101 ns) = 2.093 ns; Loc. = LAB_X30_Y14; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~278'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.195 ns" { sld_hub:sld_hub_inst|hub_tdo~275 sld_hub:sld_hub_inst|hub_tdo~278 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.197 ns) + CELL(0.390 ns) 2.680 ns sld_hub:sld_hub_inst\|hub_tdo~279 4 COMB LAB_X30_Y14 1 " "Info: 4: + IC(0.197 ns) + CELL(0.390 ns) = 2.680 ns; Loc. = LAB_X30_Y14; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~279'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "0.587 ns" { sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo~279 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.197 ns) + CELL(0.537 ns) 3.414 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LAB_X30_Y14 0 " "Info: 5: + IC(0.197 ns) + CELL(0.537 ns) = 3.414 ns; Loc. = LAB_X30_Y14; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "0.734 ns" { sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.550 ns 45.40 % " "Info: Total cell delay = 1.550 ns ( 45.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.864 ns 54.60 % " "Info: Total interconnect delay = 1.864 ns ( 54.60 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.414 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~275 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}