📄 sinewave.tan.qmsg
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{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[5\] altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0 16.421 ns memory " "Info: tco from clock \"clk\" to destination pin \"data\[5\]\" through memory \"altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0\" is 16.421 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.843 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 6.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_G1 102 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_G1; Fanout = 102; CLK Node = 'clk'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { clk } "NODE_NAME" } "" } } { "sinewave.vhd" "" { Text "E:/WUWEI/sinewave/sinewave.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.827 ns) 3.036 ns clk_temp 2 REG LC_X8_Y13_N4 17 " "Info: 2: + IC(0.910 ns) + CELL(0.827 ns) = 3.036 ns; Loc. = LC_X8_Y13_N4; Fanout = 17; REG Node = 'clk_temp'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.737 ns" { clk clk_temp } "NODE_NAME" } "" } } { "sinewave.vhd" "" { Text "E:/WUWEI/sinewave/sinewave.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.168 ns) + CELL(0.639 ns) 6.843 ns altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0 3 MEM M4K_X33_Y18 8 " "Info: 3: + IC(3.168 ns) + CELL(0.639 ns) = 6.843 ns; Loc. = M4K_X33_Y18; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.807 ns" { clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 167 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.765 ns 40.41 % " "Info: Total cell delay = 2.765 ns ( 40.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.078 ns 59.59 % " "Info: Total interconnect delay = 4.078 ns ( 59.59 % )" { } { } 0} } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "6.843 ns" { clk clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.843 ns" { clk clk~out0 clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.910ns 3.168ns } { 0.000ns 1.299ns 0.827ns 0.639ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.575 ns + " "Info: + Micro clock to output delay of source is 0.575 ns" { } { { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 167 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.003 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0 1 MEM M4K_X33_Y18 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 167 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.811 ns) 3.811 ns altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|q_a\[2\] 2 MEM M4K_X33_Y18 2 " "Info: 2: + IC(0.000 ns) + CELL(3.811 ns) = 3.811 ns; Loc. = M4K_X33_Y18; Fanout = 2; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|q_a\[2\]'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.811 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] } "NODE_NAME" } "" } } { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 38 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.327 ns) + CELL(1.865 ns) 9.003 ns data\[5\] 3 PIN PIN_A15 0 " "Info: 3: + IC(3.327 ns) + CELL(1.865 ns) = 9.003 ns; Loc. = PIN_A15; Fanout = 0; PIN Node = 'data\[5\]'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "5.192 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] data[5] } "NODE_NAME" } "" } } { "sinewave.vhd" "" { Text "E:/WUWEI/sinewave/sinewave.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.676 ns 63.05 % " "Info: Total cell delay = 5.676 ns ( 63.05 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.327 ns 36.95 % " "Info: Total interconnect delay = 3.327 ns ( 36.95 % )" { } { } 0} } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "9.003 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.003 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] data[5] } { 0.000ns 0.000ns 3.327ns } { 0.000ns 3.811ns 1.865ns } } } } 0} } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "6.843 ns" { clk clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.843 ns" { clk clk~out0 clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.910ns 3.168ns } { 0.000ns 1.299ns 0.827ns 0.639ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "9.003 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.003 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] data[5] } { 0.000ns 0.000ns 3.327ns } { 0.000ns 3.811ns 1.865ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 1.879 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 1.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.879 ns) 1.879 ns altera_reserved_tdo 2 PIN PIN_H15 0 " "Info: 2: + IC(0.000 ns) + CELL(1.879 ns) = 1.879 ns; Loc. = PIN_H15; Fanout = 0; PIN Node = 'altera_reserved_tdo'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.879 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.879 ns 100.00 % " "Info: Total cell delay = 1.879 ns ( 100.00 % )" { } { } 0} } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.879 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.879 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 1.879ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] altera_internal_jtag altera_internal_jtag~TCKUTAP 1.804 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.804 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.733 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 160 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 160; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.104 ns) + CELL(0.629 ns) 4.733 ns sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 2 REG LC_X29_Y15_N7 1 " "Info: 2: + IC(4.104 ns) + CELL(0.629 ns) = 4.733 ns; Loc. = LC_X29_Y15_N7; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns 13.29 % " "Info: Total cell delay = 0.629 ns ( 13.29 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.104 ns 86.71 % " "Info: Total interconnect delay = 4.104 ns ( 86.71 % )" { } { } 0} } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" { } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.942 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y13_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 9; PIN Node = 'altera_internal_jtag'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.840 ns) + CELL(0.102 ns) 2.942 ns sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 2 REG LC_X29_Y15_N7 1 " "Info: 2: + IC(2.840 ns) + CELL(0.102 ns) = 2.942 ns; Loc. = LC_X29_Y15_N7; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" { } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "2.942 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.102 ns 3.47 % " "Info: Total cell delay = 0.102 ns ( 3.47 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.840 ns 96.53 % " "Info: Total interconnect delay = 2.840 ns ( 96.53 % )" { } { } 0} } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "2.942 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 2.840ns } { 0.000ns 0.102ns } } } } 0} } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "2.942 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 2.840ns } { 0.000ns 0.102ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 08 16:18:07 2007 " "Info: Processing ended: Wed Aug 08 16:18:07 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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