sinewave.tan.qmsg

sinewave程序是一个正弦波发生器程序。256点查表法

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_temp " "Info: Detected ripple clock \"clk_temp\" as buffer" {  } { { "sinewave.vhd" "" { Text "E:/WUWEI/sinewave/sinewave.vhd" 22 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_temp" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0 register sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[5\] 101.0 MHz 9.901 ns Internal " "Info: Clock \"clk\" has Internal fmax of 101.0 MHz between source memory \"altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0\" and destination register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[5\]\" (period= 9.901 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.266 ns + Longest memory register " "Info: + Longest memory to register delay is 5.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0 1 MEM M4K_X33_Y18 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 167 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.811 ns) 3.811 ns altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|q_a\[2\] 2 MEM M4K_X33_Y18 2 " "Info: 2: + IC(0.000 ns) + CELL(3.811 ns) = 3.811 ns; Loc. = M4K_X33_Y18; Fanout = 2; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|q_a\[2\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.811 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] } "NODE_NAME" } "" } } { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.353 ns) + CELL(0.102 ns) 5.266 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[5\] 3 REG LC_X32_Y17_N5 3 " "Info: 3: + IC(1.353 ns) + CELL(0.102 ns) = 5.266 ns; Loc. = LC_X32_Y17_N5; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[5\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.455 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.913 ns 74.31 % " "Info: Total cell delay = 3.913 ns ( 74.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.353 ns 25.69 % " "Info: Total interconnect delay = 1.353 ns ( 25.69 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "5.266 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.266 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } { 0.000ns 0.000ns 1.353ns } { 0.000ns 3.811ns 0.102ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.027 ns - Smallest " "Info: - Smallest clock skew is -4.027 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.816 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_G1 102 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_G1; Fanout = 102; CLK Node = 'clk'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { clk } "NODE_NAME" } "" } } { "sinewave.vhd" "" { Text "E:/WUWEI/sinewave/sinewave.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.629 ns) 2.816 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[5\] 2 REG LC_X32_Y17_N5 3 " "Info: 2: + IC(0.888 ns) + CELL(0.629 ns) = 2.816 ns; Loc. = LC_X32_Y17_N5; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[5\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.517 ns" { clk sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns 68.47 % " "Info: Total cell delay = 1.928 ns ( 68.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.888 ns 31.53 % " "Info: Total interconnect delay = 0.888 ns ( 31.53 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "2.816 ns" { clk sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } { 0.000ns 0.000ns 0.888ns } { 0.000ns 1.299ns 0.629ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.843 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 6.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_G1 102 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_G1; Fanout = 102; CLK Node = 'clk'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { clk } "NODE_NAME" } "" } } { "sinewave.vhd" "" { Text "E:/WUWEI/sinewave/sinewave.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.827 ns) 3.036 ns clk_temp 2 REG LC_X8_Y13_N4 17 " "Info: 2: + IC(0.910 ns) + CELL(0.827 ns) = 3.036 ns; Loc. = LC_X8_Y13_N4; Fanout = 17; REG Node = 'clk_temp'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.737 ns" { clk clk_temp } "NODE_NAME" } "" } } { "sinewave.vhd" "" { Text "E:/WUWEI/sinewave/sinewave.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.168 ns) + CELL(0.639 ns) 6.843 ns altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0 3 MEM M4K_X33_Y18 8 " "Info: 3: + IC(3.168 ns) + CELL(0.639 ns) = 6.843 ns; Loc. = M4K_X33_Y18; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_mcj:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.807 ns" { clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 167 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.765 ns 40.41 % " "Info: Total cell delay = 2.765 ns ( 40.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.078 ns 59.59 % " "Info: Total interconnect delay = 4.078 ns ( 59.59 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "6.843 ns" { clk clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.843 ns" { clk clk~out0 clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.910ns 3.168ns } { 0.000ns 1.299ns 0.827ns 0.639ns } } }  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "2.816 ns" { clk sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } { 0.000ns 0.000ns 0.888ns } { 0.000ns 1.299ns 0.629ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "6.843 ns" { clk clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.843 ns" { clk clk~out0 clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.910ns 3.168ns } { 0.000ns 1.299ns 0.827ns 0.639ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.575 ns + " "Info: + Micro clock to output delay of source is 0.575 ns" {  } { { "db/altsyncram_mcj.tdf" "" { Text "E:/WUWEI/sinewave/db/altsyncram_mcj.tdf" 167 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "5.266 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.266 ns" { altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|q_a[2] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } { 0.000ns 0.000ns 1.353ns } { 0.000ns 3.811ns 0.102ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "2.816 ns" { clk sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] } { 0.000ns 0.000ns 0.888ns } { 0.000ns 1.299ns 0.629ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "6.843 ns" { clk clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.843 ns" { clk clk~out0 clk_temp altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.910ns 3.168ns } { 0.000ns 1.299ns 0.827ns 0.639ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|hub_tdo 119.33 MHz 8.38 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 119.33 MHz between source register \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 8.38 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.959 ns + Longest register register " "Info: + Longest register to register delay is 3.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LC_X35_Y15_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y15_N2; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.424 ns) + CELL(0.522 ns) 1.946 ns sld_hub:sld_hub_inst\|hub_tdo~276 2 COMB LC_X30_Y15_N8 1 " "Info: 2: + IC(1.424 ns) + CELL(0.522 ns) = 1.946 ns; Loc. = LC_X30_Y15_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~276'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.946 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~276 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.653 ns) 3.959 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LC_X30_Y14_N0 0 " "Info: 3: + IC(1.360 ns) + CELL(0.653 ns) = 3.959 ns; Loc. = LC_X30_Y14_N0; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "2.013 ns" { sld_hub:sld_hub_inst|hub_tdo~276 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.175 ns 29.68 % " "Info: Total cell delay = 1.175 ns ( 29.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.784 ns 70.32 % " "Info: Total interconnect delay = 2.784 ns ( 70.32 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.959 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~276 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.959 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~276 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.424ns 1.360ns } { 0.000ns 0.522ns 0.653ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.733 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 160 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 160; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.104 ns) + CELL(0.629 ns) 4.733 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X30_Y14_N0 0 " "Info: 2: + IC(4.104 ns) + CELL(0.629 ns) = 4.733 ns; Loc. = LC_X30_Y14_N0; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns 13.29 % " "Info: Total cell delay = 0.629 ns ( 13.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.104 ns 86.71 % " "Info: Total interconnect delay = 4.104 ns ( 86.71 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.733 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 160 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 160; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.104 ns) + CELL(0.629 ns) 4.733 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 2 REG LC_X35_Y15_N2 1 " "Info: 2: + IC(4.104 ns) + CELL(0.629 ns) = 4.733 ns; Loc. = LC_X35_Y15_N2; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns 13.29 % " "Info: Total cell delay = 0.629 ns ( 13.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.104 ns 86.71 % " "Info: Total interconnect delay = 4.104 ns ( 86.71 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } }  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.959 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~276 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.959 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~276 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.424ns 1.360ns } { 0.000ns 0.522ns 0.653ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\] altera_internal_jtag altera_internal_jtag~TCKUTAP 1.048 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.048 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.748 ns + Longest pin register " "Info: + Longest pin to register delay is 5.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y13_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 9; PIN Node = 'altera_internal_jtag'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.628 ns) + CELL(0.258 ns) 3.886 ns sld_hub:sld_hub_inst\|comb~67 2 COMB LC_X31_Y17_N4 5 " "Info: 2: + IC(3.628 ns) + CELL(0.258 ns) = 3.886 ns; Loc. = LC_X31_Y17_N4; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst\|comb~67'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "3.886 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.767 ns) 5.748 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\] 3 REG LC_X30_Y15_N4 2 " "Info: 3: + IC(1.095 ns) + CELL(0.767 ns) = 5.748 ns; Loc. = LC_X30_Y15_N4; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "1.862 ns" { sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "db/decode_9ie.tdf" "" { Text "E:/WUWEI/sinewave/db/decode_9ie.tdf" 32 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.025 ns 17.83 % " "Info: Total cell delay = 1.025 ns ( 17.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.723 ns 82.17 % " "Info: Total interconnect delay = 4.723 ns ( 82.17 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "5.748 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.748 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 3.628ns 1.095ns } { 0.000ns 0.258ns 0.767ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "db/decode_9ie.tdf" "" { Text "E:/WUWEI/sinewave/db/decode_9ie.tdf" 32 8 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.733 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 160 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 160; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.104 ns) + CELL(0.629 ns) 4.733 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\] 2 REG LC_X30_Y15_N4 2 " "Info: 2: + IC(4.104 ns) + CELL(0.629 ns) = 4.733 ns; Loc. = LC_X30_Y15_N4; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\]'" {  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "db/decode_9ie.tdf" "" { Text "E:/WUWEI/sinewave/db/decode_9ie.tdf" 32 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns 13.29 % " "Info: Total cell delay = 0.629 ns ( 13.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.104 ns 86.71 % " "Info: Total interconnect delay = 4.104 ns ( 86.71 % )" {  } {  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } }  } 0}  } { { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "5.748 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.748 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 3.628ns 1.095ns } { 0.000ns 0.258ns 0.767ns } } } { "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" "" { Report "E:/WUWEI/sinewave/db/sinewave_cmp.qrpt" Compiler "sinewave" "UNKNOWN" "V1" "E:/WUWEI/sinewave/db/sinewave.quartus_db" { Floorplan "E:/WUWEI/sinewave/" "" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.733 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 4.104ns } { 0.000ns 0.629ns } } }  } 0}