📄 sinewave.tan.rpt
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; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
; altera_internal_jtag~TCKUTAP ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg1 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg2 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg3 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg4 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg5 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg6 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg7 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5] ; clk ; clk ; None ; None ; 5.266 ns ;
; N/A ; 101.08 MHz ( period = 9.893 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg0 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] ; clk ; clk ; None ; None ; 5.258 ns ;
; N/A ; 101.08 MHz ( period = 9.893 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg1 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] ; clk ; clk ; None ; None ; 5.258 ns ;
; N/A ; 101.08 MHz ( period = 9.893 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg2 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] ; clk ; clk ; None ; None ; 5.258 ns ;
; N/A ; 101.08 MHz ( period = 9.893 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg3 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] ; clk ; clk ; None ; None ; 5.258 ns ;
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