sinewave.tan.rpt

sinewave程序是一个正弦波发生器程序。256点查表法

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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                               ; To                                                                                      ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 1.048 ns                         ; altera_internal_jtag                                                               ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[3] ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 16.421 ns                        ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg7 ; data[5]                                                                                 ; clk                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 1.879 ns                         ; altera_internal_jtag~TDO                                                           ; altera_reserved_tdo                                                                     ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.804 ns                         ; altera_internal_jtag                                                               ; sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3]                         ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 101.00 MHz ( period = 9.901 ns ) ; altsyncram:Mux_rtl_0|altsyncram_mcj:auto_generated|ram_block1a7~porta_address_reg7 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5]                                    ; clk                          ; clk                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 119.33 MHz ( period = 8.380 ns ) ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                            ; sld_hub:sld_hub_inst|hub_tdo                                                            ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                    ;                                                                                         ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12F256I7       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;