sio.c

uT Kernel os source code for AT91

/*
 *----------------------------------------------------------------------
 *    micro T-Kernel
 *
 *    Copyright (C) 2006-2007 by Ken Sakamura. All rights reserved.
 *    micro T-Kernel is distributed under the micro T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.00.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2007/03/26.
 *
 *----------------------------------------------------------------------
 */

#include <basic.h>

#define MSTP_CRB	(0x00fffde8UL + 1UL)
#define PB_DR	(0x00fffe3aUL + 0xd0UL)
#define SCI2_SMR	(0x00ffff88UL)
#define SCI2_BRR	(0x00ffff89UL)
#define SCI2_SCR	(0x00ffff8aUL)
#define SCI2_TDR	(0x00ffff8bUL)
#define SCI2_SSR	(0x00ffff8cUL)
#define SCI2_RDR	(0x00ffff8dUL)
#define SCI2_SCMR	(0x00ffff8eUL)


#define CPUCLK		(4000000UL)				/* CPU clock : 4MHz */
#define SYSCLK		(CPUCLK)				/* System clock (Hz) */
#define RS_BAUD_RATE	(9600)				/* 9.6kbps */

void Sci2AsyncMode( void );
char Sci2AsyncTx(unsigned char Data);
char Sci2AsyncRx(unsigned char *pData);



int sio_send_frame(const unsigned char* buf, int size)
{
	int i;

	*((unsigned char*)MSTP_CRB) &= (unsigned char)~(1U << 5);
	*((unsigned char*)PB_DR) &= ~(1UL << 0);
	Sci2AsyncMode();
	for(i = 0; i < size; i++) {
		Sci2AsyncTx(buf[i]);
	}
	*((unsigned char*)PB_DR) |= (1UL << 0);
	*((unsigned char*)SCI2_SCR) &= ~(1UL << 5);
	*((unsigned char*)SCI2_SCR) &= ~(1UL << 4);
	*((unsigned char*)MSTP_CRB) |= (1U << 5);

	return i;
}

int sio_recv_frame(unsigned char* buf, int size)
{
	int i;

	*((unsigned char*)MSTP_CRB) &= (unsigned char)~(1U << 5);
	*((unsigned char*)PB_DR) &= ~(1UL << 0);
	Sci2AsyncMode();
	for(i = 0; i < size; i++) {
		while(Sci2AsyncRx(&buf[i]) != 0) {
			;
		}
	}
	*((unsigned char*)PB_DR) |= (1UL << 0);
	*((unsigned char*)SCI2_SCR) &= ~(1UL << 5);
	*((unsigned char*)SCI2_SCR) &= ~(1UL << 4);
	*((unsigned char*)MSTP_CRB) |= (1U << 5);

	return i;
}

void sio_nop(void) {
	Asm("nop\n\tnop\n\tnop\n\tnop");
}

void Sci2AsyncMode( void )
{
	unsigned char Brr;
	unsigned long dly;

	*((unsigned char*)SCI2_SCR) = 0x00;			/* TE = 0 RE = 0 */
	*((unsigned char*)SCI2_SCMR) = 0x00;		/* LSB first */
	*((unsigned char*)SCI2_SMR) = 0x00;			/* Data8 Stop1 */
	Brr = (unsigned char)((1000000 / 64 * 2) / RS_BAUD_RATE * (CPUCLK / 1000 / 1000) +.5);
	*((unsigned char*)SCI2_BRR) = Brr;

	dly = SYSCLK / RS_BAUD_RATE;
	while ((dly--) != 0){ sio_nop(); }

	*((unsigned char*)SCI2_SCR) |= 0x30;		/* TE = 1 RE = 1 */
}

char Sci2AsyncTx(unsigned char Data)
{
	while ((*((unsigned char*)SCI2_SSR) & (1U << 7)) == 0){};
	*((unsigned char*)SCI2_TDR) = Data;
	*((unsigned char*)SCI2_SSR) &= ~(1U << 7);
	while ((*((unsigned char*)SCI2_SSR) & (1U << 2)) == 0){};
	*((unsigned char*)SCI2_SSR) &= ~(1U << 2);

	return 1;
}

char Sci2AsyncRx(unsigned char *pData)
{
	if ((*((unsigned char*)SCI2_SSR) & (1U << 4)) != 0){
		*((unsigned char*)SCI2_SSR) &= ~(1U << 4);
		return 1;
	}
	if ((*((unsigned char*)SCI2_SSR) & (1U << 3)) != 0){
		*((unsigned char*)SCI2_SSR) &= ~(1U << 3);
		return 2;
	}
	if ((*((unsigned char*)SCI2_SSR) & (1U << 5)) != 0){
		*((unsigned char*)SCI2_SSR) &= ~(1U << 5);
		return 3;
	}

	if ((*((unsigned char*)SCI2_SSR) & (1U << 6)) != 0){
		*pData = *((unsigned char*)SCI2_RDR);
		*((unsigned char*)SCI2_SSR) &= ~(1U << 6);
		return 0;
	}

	return -1;
}