📄 at91sam7se512_lfbga144.bsd
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"pb5 : C3," &
"pb6 : B1," &
"pb7 : A1," &
"pb8 : A2," &
"pb9 : A3," &
"pc0 : K4," &
"pc1 : L4," &
"pc10 : J2," &
"pc11 : K1," &
"pc12 : J1," &
"pc13 : H3," &
"pc14 : H2," &
"pc15 : H1," &
"pc16 : G2," &
"pc17 : G3," &
"pc18 : G1," &
"pc19 : F3," &
"pc2 : K3," &
"pc20 : F2," &
"pc21 : F1," &
"pc22 : E1," &
"pc23 : E2," &
"pc3 : M3," &
"pc4 : L3," &
"pc5 : M2," &
"pc6 : K2," &
"pc7 : L2," &
"pc8 : M1," &
"pc9 : G4," &
"tdo : D4," &
"xout : M10," &
"sdck : L1," &
"ad4 : G10," &
"ad5 : F10," &
"ad6 : J7," &
"ad7 : J8," &
"advref : L8";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of tck: signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of tdi: signal is true;
attribute TAP_SCAN_MODE of tms: signal is true;
attribute TAP_SCAN_OUT of tdo: signal is true;
attribute TAP_SCAN_RESET of nrst : signal is true;
-- Specifies the compliance enable patterns for the design.
-- It lists a set of design ports and the values that they
-- should be set to, in order to enable compliance to IEEE
-- Std 1149.1
attribute COMPLIANCE_PATTERNS of AT91SAM7SE512: entity is
"(jtagsel, test) (10)";
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of AT91SAM7SE512: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of AT91SAM7SE512: entity is
"BYPASS (111, 100, 110)," &
"EXTEST (000, 011)," &
"SAMPLE (001)," &
"IDCODE (010)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of AT91SAM7SE512: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of AT91SAM7SE512: entity is
"0000" & -- 4-bit version number
"0101101100010100" & -- 16-bit part number
"00000011111" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of AT91SAM7SE512: entity is
"BYPASS (BYPASS)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of AT91SAM7SE512: entity is 354;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of AT91SAM7SE512: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"353 (BC_1, sdck, output2, X), " &
"352 (BC_1, pc8, input, X), " &
"351 (BC_1, pc8, output3, X, 350, 1, Z), " &
"350 (BC_1, *, controlr, 1), " &
"349 (BC_0, *, internal, X), " &
"348 (BC_1, pc7, input, X), " &
"347 (BC_1, pc7, output3, X, 346, 1, Z), " &
"346 (BC_1, *, controlr, 1), " &
"345 (BC_0, *, internal, X), " &
"344 (BC_1, pc6, input, X), " &
"343 (BC_1, pc6, output3, X, 342, 1, Z), " &
"342 (BC_1, *, controlr, 1), " &
"341 (BC_0, *, internal, X), " &
"340 (BC_1, pc5, input, X), " &
"339 (BC_1, pc5, output3, X, 338, 1, Z), " &
"338 (BC_1, *, controlr, 1), " &
"337 (BC_0, *, internal, X), " &
"336 (BC_1, pc4, input, X), " &
"335 (BC_1, pc4, output3, X, 334, 1, Z), " &
"334 (BC_1, *, controlr, 1), " &
"333 (BC_0, *, internal, X), " &
"332 (BC_1, pc3, input, X), " &
"331 (BC_1, pc3, output3, X, 330, 1, Z), " &
"330 (BC_1, *, controlr, 1), " &
"329 (BC_0, *, internal, X), " &
"328 (BC_1, pc2, input, X), " &
"327 (BC_1, pc2, output3, X, 326, 1, Z), " &
"326 (BC_1, *, controlr, 1), " &
"325 (BC_0, *, internal, X), " &
"324 (BC_1, pc1, input, X), " &
"323 (BC_1, pc1, output3, X, 322, 1, Z), " &
"322 (BC_1, *, controlr, 1), " &
"321 (BC_0, *, internal, X), " &
"320 (BC_1, pc0, input, X), " &
"319 (BC_1, pc0, output3, X, 318, 1, Z), " &
"318 (BC_1, *, controlr, 1), " &
"317 (BC_0, *, internal, X), " &
"316 (BC_1, pa31, input, X), " &
"315 (BC_1, pa31, output3, X, 314, 1, Z), " &
"314 (BC_1, *, controlr, 1), " &
"313 (BC_0, *, internal, X), " &
"312 (BC_1, pa30, input, X), " &
"311 (BC_1, pa30, output3, X, 310, 1, Z), " &
"310 (BC_1, *, controlr, 1), " &
"309 (BC_0, *, internal, X), " &
"308 (BC_1, pa29, input, X), " &
"307 (BC_1, pa29, output3, X, 306, 1, Z), " &
"306 (BC_1, *, controlr, 1), " &
"305 (BC_0, *, internal, X), " &
"304 (BC_1, pa28, input, X), " &
"303 (BC_1, pa28, output3, X, 302, 1, Z), " &
"302 (BC_1, *, controlr, 1), " &
"301 (BC_0, *, internal, X), " &
"300 (BC_1, pa27, input, X), " &
"299 (BC_1, pa27, output3, X, 298, 1, Z), " &
"298 (BC_1, *, controlr, 1), " &
"297 (BC_0, *, internal, X), " &
"296 (BC_1, pa26, input, X), " &
"295 (BC_1, pa26, output3, X, 294, 1, Z), " &
"294 (BC_1, *, controlr, 1), " &
"293 (BC_0, *, internal, X), " &
"292 (BC_1, pa25, input, X), " &
"291 (BC_1, pa25, output3, X, 290, 1, Z), " &
"290 (BC_1, *, controlr, 1), " &
"289 (BC_0, *, internal, X), " &
"288 (BC_1, pa24, input, X), " &
"287 (BC_1, pa24, output3, X, 286, 1, Z), " &
"286 (BC_1, *, controlr, 1), " &
"285 (BC_0, *, internal, X), " &
"284 (BC_1, pa23, input, X), " &
"283 (BC_1, pa23, output3, X, 282, 1, Z), " &
"282 (BC_1, *, controlr, 1), " &
"281 (BC_0, *, internal, X), " &
"280 (BC_1, pa22, input, X), " &
"279 (BC_1, pa22, output3, X, 278, 1, Z), " &
"278 (BC_1, *, controlr, 1), " &
"277 (BC_0, *, internal, X), " &
"276 (BC_1, pa21, input, X), " &
"275 (BC_1, pa21, output3, X, 274, 1, Z), " &
"274 (BC_1, *, controlr, 1), " &
"273 (BC_0, *, internal, X), " &
"272 (BC_1, pa20, input, X), " &
"271 (BC_1, pa20, output3, X, 270, 1, Z), " &
"270 (BC_1, *, controlr, 1), " &
"269 (BC_0, *, internal, X), " &
"268 (BC_1, pa19, input, X), " &
"267 (BC_1, pa19, output3, X, 266, 1, Z), " &
"266 (BC_1, *, controlr, 1), " &
"265 (BC_0, *, internal, X), " &
"264 (BC_1, pa18, input, X), " &
"263 (BC_1, pa18, output3, X, 262, 1, Z), " &
"262 (BC_1, *, controlr, 1), " &
"261 (BC_0, *, internal, X), " &
"260 (BC_1, pa17, input, X), " &
"259 (BC_1, pa17, output3, X, 258, 1, Z), " &
"258 (BC_1, *, controlr, 1), " &
"257 (BC_0, *, internal, X), " &
"256 (BC_1, pa16, input, X), " &
"255 (BC_1, pa16, output3, X, 254, 1, Z), " &
"254 (BC_1, *, controlr, 1), " &
"253 (BC_0, *, internal, X), " &
"252 (BC_1, pa15, input, X), " &
"251 (BC_1, pa15, output3, X, 250, 1, Z), " &
"250 (BC_1, *, controlr, 1), " &
"249 (BC_0, *, internal, X), " &
"248 (BC_1, pa14, input, X), " &
"247 (BC_1, pa14, output3, X, 246, 1, Z), " &
"246 (BC_1, *, controlr, 1), " &
"245 (BC_0, *, internal, X), " &
"244 (BC_1, pa13, input, X), " &
"243 (BC_1, pa13, output3, X, 242, 1, Z), " &
"242 (BC_1, *, controlr, 1), " &
"241 (BC_0, *, internal, X), " &
"240 (BC_1, pa12, input, X), " &
"239 (BC_1, pa12, output3, X, 238, 1, Z), " &
"238 (BC_1, *, controlr, 1), " &
"237 (BC_0, *, internal, X), " &
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