modetbl.cpp

SM501基于ARMV4/ARMV4I平台

	{ 1344, 1024, 1048, 136, POSITIVE, 628, 600, 601, 4, POSITIVE,
	  50600000, 37679, 60 },

	// 1024 x 768
	{ 1344, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE,
	  65000000, 48363, 60 },
	{ 1328, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE,
	  75000000, 56476, 70 },
	{ 1312, 1024, 1040,  96, POSITIVE, 800, 768, 769, 3, POSITIVE,
	  78750000, 60023, 75 },
	{ 1376, 1024, 1072,  96, POSITIVE, 808, 768, 769, 3, POSITIVE,
	  94500000, 68677, 85 },

	// 1280 x 960
	{ 1688, 1280, 1328, 112, POSITIVE, 1000, 960, 962, 3, POSITIVE,
	  101000000, 60000, 60 },

	// 1280 x 1024
	{ 1688, 1280, 1328, 112, POSITIVE, 1066, 1024, 1025, 3, POSITIVE,
	  108000000, 63981, 60 },

	// End of table.
	{ 0, 0, 0, 0, NEGATIVE, 0, 0, 0, 0, NEGATIVE, 0, 0, 0 },
};

//
// SetModeHardware
//
// Set hardware registers for the requested mode 
//
// Inputs: 		modeId	= The Id of the mode (not the same as mode number)
//
void SMI::SetModeHardware(int modeId)
{
	mode_table_t *vesaMode, mode;
	reg_table_t register_table;
	long clock = 0;
	unsigned long value;
	unsigned long gate;

	if (rev() == 0xA0)
	{
		if (m_SMISettings.m_nTestClock == 0) 
			m_SMISettings.m_nTestClock = 133000000L;
	}

	clock = (long) m_SMISettings.m_nTestClock;

	// m_pMode->frequency = 75;
	vesaMode = findMode(mode_table,	m_SMISettings.m_dwCxPanel, m_SMISettings.m_dwCyPanel,
					m_pMode->frequency);
	if (vesaMode == NULL)
	{
		RETAILMSG (1, (_T("SMIVGX - Mode not found (modeId = %d, %dx%d@%d)\r\n"), 
			modeId, m_SMISettings.m_dwCxPanel, m_SMISettings.m_dwCyPanel,
					m_SMISettings.m_nFrequency));
		return;
	}

	// Set mode on panel and CRT.
	adjustMode(vesaMode, &mode, PANEL, clock);
    setModeRegisters(&register_table, &mode, PANEL, m_nScreenBpp, clock);
    programMode(&register_table);

#ifdef MULTIMONEMU_ENABLE
	if (m_SMISettings.m_nDualMonEnabled == 0)
#endif //MULTIMONEMU_ENABLE
	{
        // Set mode on CRT only if requested in registry
        if (m_SMISettings.m_nDisplayType & CRT_OUTPUT)
        {
            setModeRegisters(&register_table, &mode, CRT, m_nScreenBpp, clock);
            programMode(&register_table);

            // Let CRT display panel data.
            value = peekRegisterDWord(CRT_DISPLAY_CTRL);
            value = FIELD_SET(value, CRT_DISPLAY_CTRL, SELECT, PANEL);
            value = FIELD_SET(value, CRT_DISPLAY_CTRL, PLANE, DISABLE);
            pokeRegisterDWord(CRT_DISPLAY_CTRL, value);

            // Turn off panel if DisplayType = 2 (CRT only) in registry
            if (!(m_SMISettings.m_nDisplayType & PANEL_OUTPUT))
            {
                panelPowerSequence(PANEL_OFF, 4);
            }
        }
        else
        {
            // Let CRT display CRT data because hardware will route panel data
            // to CRT by default.
            value = peekRegisterDWord(CRT_DISPLAY_CTRL);
            value = FIELD_SET(value, CRT_DISPLAY_CTRL, SELECT, CRT);
            value = FIELD_SET(value, CRT_DISPLAY_CTRL, PLANE, ENABLE);
            pokeRegisterDWord(CRT_DISPLAY_CTRL, value);
        }
	}

	// Set up memory clock and gates.
	gate = peekRegisterDWord(CURRENT_POWER_GATE);
	clock = peekRegisterDWord(CURRENT_POWER_CLOCK);
	if (rev() == 0xA0)
	{
		gate = 0xFFFFFFFF; //0x0002181F;
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SELECT, 288);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_DIVIDER, 1);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SHIFT, 1);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SELECT, 288);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_DIVIDER, 1);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SHIFT, 1);

	}
	else // RevB++
	{
		if (m_SMISettings.m_bCSCDisabled)
			gate = FIELD_SET(gate, CURRENT_POWER_GATE, CSC, DISABLE);
		else
			gate = FIELD_SET(gate, CURRENT_POWER_GATE, CSC, ENABLE);

		gate = FIELD_SET(gate, CURRENT_POWER_GATE, 2D,  ENABLE);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SELECT, 288);
		//clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_DIVIDER, 3);
		//clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SHIFT, 0);
		// Change MCLK to 72MHz
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_DIVIDER, 1);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SHIFT, 2);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SELECT, 288);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_DIVIDER, 1);
		clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SHIFT, 1);
	}
#if CMDLIST_IN_SYS_MEM
#if CMDLIST_CEPC
    //VoyagerGX RevAA PCI bus master only run Engine clock 72MHz
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SELECT, 288);
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_DIVIDER, 1);
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SHIFT, 2);
#else //CMDLIST_CEPC
#if 0
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SELECT, 336);
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_DIVIDER, 3);
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SHIFT, 0);
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SELECT, 336);
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_DIVIDER, 1);
    clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SHIFT, 1);
	POKE_32(1, 0x00111120); //set bus clock to 112MHz
#else
	POKE_32(SYSTEM_DRAM_CTRL, 0x00080800); //set bus clock to 96MHz
#endif
#endif //CMDLIST_CEPC
#endif //CMDLIST_IN_SYS_MEM

	setPower(gate, clock);

	// Reset panel frame buffer address to 0.
	pokeRegisterDWord(PANEL_FB_ADDRESS,
					  FIELD_SET(0, PANEL_FB_ADDRESS, STATUS, PENDING) |
					  FIELD_SET(0, PANEL_FB_ADDRESS, EXT, LOCAL) |
					  FIELD_VALUE(0, PANEL_FB_ADDRESS, ADDRESS, 0));

	value = PEEK_32(DE_STRETCH_FORMAT);
	value = FIELD_SET(value, DE_STRETCH_FORMAT, PATTERN_XY, NORMAL);
	value = FIELD_VALUE(value, DE_STRETCH_FORMAT, PATTERN_Y, 0);
	value = FIELD_VALUE(value, DE_STRETCH_FORMAT, PATTERN_X, 0);
	value = FIELD_VALUE(value, DE_STRETCH_FORMAT, ADDRESSING, 5);
	switch (m_nScreenBpp)
	{
		case 8:
			value = FIELD_SET(value, DE_STRETCH_FORMAT, PIXEL_FORMAT, 8);
			break;
		case 16:
			value = FIELD_SET(value, DE_STRETCH_FORMAT, PIXEL_FORMAT, 16);
			break;
		case 32:
			value = FIELD_SET(value, DE_STRETCH_FORMAT, PIXEL_FORMAT, 32);
			break;
	}
	POKE_32(DE_STRETCH_FORMAT, value);

	// Setup Panning
	m_nPanningX = m_SMISettings.m_dwPanningX;
	m_nPanningY = m_SMISettings.m_dwPanningY;

	if (((DWORD)m_nScreenWidthSave > m_SMISettings.m_dwCxPanel) ||
		((DWORD)m_nScreenHeightSave > m_SMISettings.m_dwCyPanel))
	{
		// Set the pitch for the screen width.
		value = PEEK_32(PANEL_FB_WIDTH);
		value = FIELD_VALUE(value, PANEL_FB_WIDTH, OFFSET, m_nScreenStride);
		POKE_32(PANEL_FB_WIDTH, value);

		POKE_32(PANEL_WINDOW_WIDTH,
	  	  	FIELD_VALUE(0, PANEL_WINDOW_WIDTH, WIDTH, m_nScreenWidthSave-1) |
			FIELD_VALUE(0, PANEL_WINDOW_WIDTH, X, m_nPanningX) );

		POKE_32(PANEL_WINDOW_HEIGHT,
		  	FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, HEIGHT, m_nScreenHeightSave-1) |
		  	FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, Y, m_nPanningY) );
	}

	POKE_32(PANEL_PAN_CTRL, 0x00000000);	// pixel panning
	POKE_32(PANEL_COLOR_KEY, 0x00000000);	// mask, color key


	POKE_32(DE_WRAP,
		FIELD_VALUE(0, DE_WRAP, X, m_nScreenWidthSave ) |
		FIELD_VALUE(0, DE_WRAP, Y, 0xFFFF ) |
		0 );

    POKE_32(DE_CLIP_TL,
		FIELD_INIT(DE_CLIP_TL, STATUS, DISABLE)); //Disable clip at init

	POKE_32(VIDEO_INITIAL_SCALE, 
		FIELD_VALUE(0, VIDEO_INITIAL_SCALE, FB_1, 0) |
		FIELD_VALUE(0, VIDEO_INITIAL_SCALE, FB_0, 0) |
		0);

	POKE_32(DE_MASKS,
		FIELD_VALUE(0, DE_MASKS, BYTE_MASK, 0xFFFF ) |
		FIELD_VALUE(0, DE_MASKS, BIT_MASK, 0xFFFF ) |
		0 );

	POKE_32(DE_COLOR_COMPARE_MASK,
		FIELD_VALUE(0, DE_COLOR_COMPARE_MASK, MASKS, 0xFFFFFFFF ) |
		0 );
	POKE_32(DE_COLOR_COMPARE,
		FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, 0xFFFFFFFF ) |
		0 );

    if (m_SMISettings.isPanelType(SSP_HITACHI320x240MSTN) && m_SMISettings.m_dwCxPanel == 320)
	{
		setClock(0x120b0801);
		pokeRegisterDWord(PANEL_DISPLAY_CTRL, 0x0f0d0105); 
		pokeRegisterDWord(PANEL_HORIZONTAL_TOTAL, 0x0164013f);
		pokeRegisterDWord(PANEL_HORIZONTAL_SYNC, 0x0018014f);
		pokeRegisterDWord(PANEL_VERTICAL_TOTAL, 0x010800f0);
		pokeRegisterDWord(PANEL_VERTICAL_SYNC, 0x00020104);
	}

	//Plexus requested special Hsync and Vsync timings for 800x600 TFT panel.
	if (m_SMISettings.isPanelType(SSP_PLEXUS800x600TFT))	
	{
		pokeRegisterDWord(PANEL_HORIZONTAL_SYNC, 0x00d4037f);
		pokeRegisterDWord(PANEL_VERTICAL_SYNC, 0x00180258);
	}																						

	if (m_SMISettings.isPanelSettings(SSS_ANY))
	{
		DWORD dwIdx = 1;

		// Note: All this if checking has to check from lower index to higher index
		if (m_SMISettings.isPanelSettings(SSS_PANEL_HORIZONTAL_TOTAL))
			pokeRegisterDWord(PANEL_HORIZONTAL_TOTAL, m_SMISettings.getPanelSettings(dwIdx++));

		if (m_SMISettings.isPanelSettings(SSS_PANEL_HORIZONTAL_SYNC))
			pokeRegisterDWord(PANEL_HORIZONTAL_SYNC, m_SMISettings.getPanelSettings(dwIdx++));

		if (m_SMISettings.isPanelSettings(SSS_PANEL_VERTICAL_TOTAL))
			pokeRegisterDWord(PANEL_VERTICAL_TOTAL, m_SMISettings.getPanelSettings(dwIdx++));

		if (m_SMISettings.isPanelSettings(SSS_PANEL_VERTICAL_SYNC))
			pokeRegisterDWord(PANEL_VERTICAL_SYNC, m_SMISettings.getPanelSettings(dwIdx++));

		if (m_SMISettings.isPanelSettings(SSS_POWER_MODE_CLOCK))
			setClock(m_SMISettings.getPanelSettings(dwIdx++));

		if (m_SMISettings.isPanelSettings(SSS_PANEL_DISPLAY_CTRL))
			pokeRegisterDWord(PANEL_DISPLAY_CTRL, m_SMISettings.getPanelSettings(dwIdx++)); 
	}

/*
	// Enable ZV Port lines - cannot enable because HW issues

	value = PEEK_32(GPIO_MUX_LOW);
	value = FIELD_SET(value, GPIO_MUX_LOW, 23, ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_LOW, 22, ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_LOW, 21, ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_LOW, 20, ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_LOW, 19, ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_LOW, 18, ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_LOW, 17, ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_LOW, 16, ZVPORT);
	POKE_32(GPIO_MUX_LOW, value);

	value = PEEK_32(GPIO_MUX_HIGH);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 63, CRT_ZVPORT_FPDATA);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 62, CRT_ZVPORT_FPDATA);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 61, CRT_ZVPORT_FPDATA);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 60, CRT_ZVPORT_FPDATA);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 59, CRT_ZVPORT_FPDATA);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 58, CRT_ZVPORT_FPDATA);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 57, CRT_ZVPORT);
	value = FIELD_SET(value, GPIO_MUX_HIGH, 56, CRT_ZVPORT);
	POKE_32(GPIO_MUX_HIGH, value);
*/
	//RETAILMSG(1,(TEXT("SMI - Modetbl.cpp - WaitForVBlank---\n")));
	//WaitForVBlank();
	//WaitForVBlank();
	//WaitForVBlank();
	//WaitForVBlank();
	//RETAILMSG(1,(TEXT("SMI - Modetbl.cpp - WaitForVBlank+++\n")));

	// Configure PCI Burst
	//value = peekRegisterDWord(SYSTEM_CTRL);
	//value = FIELD_SET(value, SYSTEM_CTRL, PCI_BURST, ENABLE);
	//value = FIELD_SET(value, SYSTEM_CTRL, PCI_MASTER, START);
	//value = FIELD_SET(value, SYSTEM_CTRL, PCI_BURST_READ, ENABLE);
	//value = FIELD_SET(value, SYSTEM_CTRL, PCI_SLAVE_BURST_READ_SIZE, 8);
	//value = FIELD_SET(value, SYSTEM_CTRL, LATENCY_TIMER, ENABLE);
	//value = 0x22008030;
	//pokeRegisterDWord(SYSTEM_CTRL, value);

	//RETAILMSG(1,(TEXT("SMI - Modetbl.cpp - PCIBurst+++\n")));
}