top.v

VGA/LCD Corev2.0Specifications

//-----------------------------------------------------------------------------
//
// Author: John Clayton
// Date  : Aug.   20, 2002
// Update: Aug.   20, 2002 Obtained this file from "build_12" project.
// Update: Sep.   12, 2002 Tested rs232_syscon with tracking autobaud circuit
//                         inside it, so that the whole system can run at
//                         different clock speeds.  Synchronizing to high
//                         baud rates at low clock speeds doesn't work (as
//                         expected!)
//
// Description
//-----------------------------------------------------------------------------
// This targets an XC2S200 board which was created for educational purposes.
//
// There are:
//    8  LEDs (led[7:0])
//    4  switches (switch[3:0])
//    1  clock of 32.000 MHz clock, present on GCLK1
//    1  clock of 49.152 MHz clock, present on GCLK0
//    4  lines of ps2 clock input (port A in documentation notes)
//    4  lines of ps2 data input (port A in documentation notes)
//    16 lines of LCD panel control (port B in documentation notes)
//    2  lines of rs232 serial connection (port C in documentation notes)
//-----------------------------------------------------------------------------
//
// NOTE: This build is for testing out an automatic BAUD rate generator
//
// The following 'include line must be used with Synplify to create EDIF
// The line must be commented for ModelSim.
//`include "d:\synplicity\synplify_70\lib\xilinx\virtex.v"

module top (
  sys_clk_0,
  sys_clk_1,
  switch,
  led,
  lcd_drive,
  rs232_rxd,
  rs232_txd,
  port_e,
  port_f,
  dat_o
  );

// I/O declarations
input sys_clk_0;      // 49.152 MHz
input sys_clk_1;      // 32.000 MHz
input [3:0] switch;
input rs232_rxd;
input [13:0] port_f;

output [7:0] led;
output [15:0] lcd_drive;
output rs232_txd;
output [13:0] port_e;
output [15:0] dat_o;

// Internal signal declarations

wire [4:0] r0_wire;  // "Read" regs.  Used to "hold" pin locations, so that
                     // the synthesis tools do not complain about these pins
                     // being present in the constraints file and not in the
                     // design...

wire [13:0] input_f = ~port_f;  // Port f input inverted (bcd thumbwheel)

     // System Clock signals
wire sys_clk_variable;
wire sys_clk_variable_half;
wire sys_clk_lcd;
//wire sys_clk_half;
wire [8:0] sys_clk_freq;
reg  [3:0] clk_count0;  // Counter used to generate clock
reg  [3:0] clk_count1;  // Counter used to generate clock

     // Signals from risc processor
wire [15:0] risc_aux_adr;     // AUX (expansion) bus
wire        risc_aux_we;      // AUX we
wire [15:0] risc_prog_dat;    // Program data
wire [12:0] risc_prog_adr;    // (Up to 8k words possible)
wire [8:0]  risc_ram_adr;     // RAM file address
wire [7:0]  risc_ram_dat_o;   // RAM file data
wire [7:0]  risc_ram_dat_i;   // RAM file data
wire        risc_ram_we;      // RAM we
wire        risc_stb;         // Clock enable for risc processor

     // Signals from rs232_syscon
wire [15:0] adr;        // A side address
wire [7:0] dat;         // A side data
wire we;
wire stb;
wire rst;
wire master_br;

    // Address decode signals
wire       code_space;  // High for access to code space (AUX bus)
wire       rgb_space;   // High for access to rgb space (AUX bus)
wire       io_space;    // High for access to I/O space (AUX bus)
wire [2:0] io_sel;      // 1 of these is active high for I/O space accesses

    // Hardware breakpoint and single stepping signals
wire [12:0] break_prog_adr;  // For hardware breakpoint on prog. adr
wire [13:0] break_prog_dat;  // For hardware breakpoint on prog. dat
wire [ 1:0] break_enable;    // bit 1: enables dat BP, bit 0: enables adr BP
wire        breakpoint;      // 1 = any breakpoint condition encountered.
reg  [ 5:0] step_count;      // Number of steps remaining to execute
wire [ 5:0] clocks_to_step;  // Desired number of steps to execute
wire        begin_stepping;       // Automatically resets itself when written!
wire        stepping_active;      // 1 during single stepping
wire        reset_single_stepper; // 1 during breakpoint or reset
wire [ 1:0] processor_control; // Contains two signals (renamed below)
wire        run_free;          // Allows processor to run constantly
wire        forced_reset;      // Forces the processor into reset
wire        bus_rdy;           // 1 = processor can execute this clock cycle.


    // A side RAM signals
wire [7:0] code_ram_dat_o;
wire [2:0] rgb_ram_dat_o;
wire [7:0] regfile_ram_dat_o;

    // B side (Peripheral side) RAM signals
wire [2:0]  pixel_dat;
wire [13:0] pixel_adr;   // (12288 pixels addressed)

    // Other...
wire reset = switch[0];  // Simply a renaming exercise

//--------------------------------------------------------------------------
// Clock generation
//--------------------------------------------------------------------------

clock_multiply
  clock_block
  (
   .clkin(sys_clk_0),
   .reset(1'b0),
   .clk2x(),
   .clk4x(sys_clk_4x),
   .locked()
   );

// This uses up a GCLK resource.
always @(posedge sys_clk_variable)
begin: clock_block_1
  clk_count1 <= clk_count1 + 1;
end
assign sys_clk_variable_half = clk_count1[0];

//--------------------------------------------------------------------------
// Instantiations
//--------------------------------------------------------------------------

// This is for monitoring signals using a logic analyzer
assign dat_o = {
                0
//                sys_clk_lcd,
//                sys_clk_variable_half  // DDS frequency is output here.
                };

assign port_e = 0;        // Don't drive the stepper for now.

// This block generates a divided version of the fast clock
// (It is put into a separate module to facilitate adding timing
//  constraints to it...)
clock_divider #(3)
  clock_block_0
  (
   .clk_i(sys_clk_4x),
   .clk_o(sys_clk_lcd)
   );


// This block generates a variable frequency system clock
assign sys_clk_freq = input_f[7:0] + 1;
square_wave_dds #(
                  9       // DDS counter length
                  )
dds1
   (
    .clk(sys_clk_4x),
    .clk_en(switch[3]),
    .reset(reset),
    .frequency(sys_clk_freq),
    .clk_out(sys_clk_variable)
    );


// This block runs the flat panel display (5x5 pixels)
vga_128_by_92 lcd_block (
  .lcd_clk(sys_clk_lcd),
  .lcd_reset(reset),
  .pixel_dat_i(pixel_dat),
  .pixel_adr_o(pixel_adr),
  .lcd_drive(lcd_drive)
  );

// This block is the risc microcontroller
assign risc_stb = (bus_rdy || rst);
risc16f84_clk2x 
  processor1
  (
   .prog_dat_i(risc_prog_dat[13:0]),  // [13:0] ROM read data
   .prog_adr_o(risc_prog_adr),        // [12:0] ROM address
   .ram_dat_i(risc_ram_dat_i),        // [7:0] RAM read data
   .ram_dat_o(risc_ram_dat_o),        // [7:0] RAM write data
   .ram_adr_o(risc_ram_adr),          // [8:0] RAM address
   .ram_we_o(risc_ram_we),            // RAM write strobe (H active)
   .aux_adr_o(risc_aux_adr),    // [15:0] Auxiliary address bus
   .aux_dat_io(dat),            // [7:0] AUX data (shared w/rs232_syscon)
   .aux_we_o(risc_aux_we),      // Auxiliary write strobe (H active)
   .int0_i(1'b0),               // PORT-B(0) INT
   .reset_i(rst),               // Power-on reset (H active)
   .clk_en_i(risc_stb),         // Clock enable for all clocked logic
   .clk_i(sys_clk_variable_half)      // Clock input
   );


// This block is the rs232 user interface for debugging, programming etc.
rs232_syscon #(
               4,             // Number of Hex digits for addresses.
               2,             // Number of Hex digits for data.
               2,             // Number of Hex digits for quantity.
               16,            // Characters in the input buffer
               4,             // Bits in the buffer pointer
               63,            // Clocks before watchdog timer expires
               6,             // Bits in watchdog timer
               8,             // Number of data fields displayed per line
               3,             // Number of bits in the fields counter
               2              // Number of bits in the digits counter
               )
  syscon_1 (                  // instance name
  .clk_i(sys_clk_variable_half),
  .reset_i(reset),
  .master_bg_i(master_br),
  .ack_i(code_space || rgb_space || ram_space || io_space),
  .err_i(1'b0),
  .master_adr_i(risc_aux_adr),
  .master_stb_i(risc_stb),