📄 cs8900a.h
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/****************************************************************************/
/* */
/* FILENAME VERSION */
/* */
/* CS8900A.H 0.91 */
/* */
/* DESCRIPTION */
/* */
/* This file contains the definitions and macros necessary for the */
/* CS8900A driver. */
/* */
/* DATA STRUCTURES */
/* */
/* none */
/* */
/* FUNCTIONS */
/* */
/* none */
/* */
/* DEPENDENCIES */
/* */
/* none */
/* */
/* HISTORY */
/* */
/* NAME DATE REMARKS */
/* */
/* 02/17/96 Inital version. (Version 1.0) */
/* 03/11/96 This file did not change for version 1.0a */
/* */
/****************************************************************************/
#ifndef CS8900A_H
#define CS8900A_H
#include "dev.h"
#include "target.h"
typedef char int8; /* 1 1 */
typedef unsigned char uint8; /* 1 1 */
typedef short int int16; /* 2 2 */
typedef unsigned short uint16; /* 2 2 */
typedef long int int32; /* 4 4 */
typedef unsigned long uint32; /* 4 4 */
/* This structure is used to keep track of extended data that is required for
each registered CS8900A device. */
typedef struct _CS8900A_XDATA
{
/* Receive errors. */
uint16 OVW_Error_Count;
uint16 CRC_Error_Count;
uint16 FAE_Error_Count;
uint16 FIFO_Error_Count;
uint16 MPA_Error_Count;
/* Transmit errors. */
uint16 COLL_Error_Count;
uint16 ABT_Error_Count;
uint16 CRS_Error_Count;
uint16 FU_Error_Count;
uint16 CDH_Error_Count;
uint16 OWC_Error_Count;
/* Page data. */
uint8 Next_Page;
// unsigned int cur_rx, cur_tx; /* Index into the Rx buffer */
// unsigned int dirty_tx, tx_flag; /* of next Rx pkt. */
/* The saved address of a sent-in-place packet/buffer, for skfree(). */
// unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
// unsigned char *rx_ring;
// unsigned char *tx_bufspc; /* Tx bounce buffer region. */
// unsigned int tx_full; /* The Tx queue is full. */
} CS8900A_XDATA;
#define OUTW(offset, value) outport ((int16)offset, (int16)value)
#define INW(offset) (uint16)inport ((uint16)offset)
#define OUTB(offset, value) outp ((int16)offset, (uint8)value)
#define INB(offset) (uint8)inp ((int16)offset)
#define CS8900A_pPacketPage 0x86000000
#define EP7211_Register_Base 0x80000000
#define EP7211_intmask1_Offset 0x280
#define Eint3_Enable 0x0080
#define CS8900AInMemoryMode 0
/* Description of header of each packet in receive area of memory */
#define RBUF_STAT 0 /* Received frame status */
#define RBUF_NXT_PG 1 /* Page after this frame */
#define RBUF_SIZE_LO 2 /* Length of this frame */
#define RBUF_SIZE_HI 3 /* Length of this frame (hi byte) */
#define RBUF_HDR_LEN 4 /* Length of above header area */
#define PSTART 0x46 //whether or not collision to IRQ_VECTOR in follows.
#define PSTOP 0x80
#define TX_PAGE 0x40
#define SIZE_OF_CRC 4
#define MAX_FRAME_SIZE 256
/***********************************************************************************/
#define FAILURE (-1)
#define SUCCESS 0
#define TRUE 1
#define FALSE 0
#define MAXLOOP 0x8888
#define HEADER_LENGTH 14
#define SIGNATURE_PKTPG_PTR 0x3000
#define EISA_NUM_CRYSTAL 0x630E
#define PROD_ID_MASK 0xE000
#define PROD_ID_CS8900 0x0000
#define PROD_ID_CS8920 0x4000
#define PROD_ID_CS892X 0x6000
#define PROD_REV_MASK 0x1F00
#define FRAME_TYPE_IP 0x0800
#define FRAME_TYPE_ARP 0x0806
#define FRAME_TYPE_RARP 0x8035
#define FRAME_TYPE_NETWARE 0x8137
#define MAXTXREQ 16
#define BSP_CS8900_IO_BASE 0x86000300
/* IO Port Addresses */
#define PORT_RXTX_DATA (BSP_CS8900_IO_BASE+0x00)
#define PORT_RXTX_DATA_1 (BSP_CS8900_IO_BASE+0x02)
#define PORT_TX_CMD (BSP_CS8900_IO_BASE+0x04)
#define PORT_TX_LENGTH (BSP_CS8900_IO_BASE+0x06)
#define PORT_ISQ (BSP_CS8900_IO_BASE+0x08)
#define PORT_PKTPG_PTR (BSP_CS8900_IO_BASE+0x0A)
#define PORT_PKTPG_DATA (BSP_CS8900_IO_BASE+0x0C)
#define PORT_PKTPG_DATA_1 (BSP_CS8900_IO_BASE+0x0E)
/*
#define PORT_RXTX_DATA (BSP_CS8900_IO_BASE+0x00)
#define PORT_RXTX_DATA_1 (BSP_CS8900_IO_BASE+0x04)
#define PORT_TX_CMD (BSP_CS8900_IO_BASE+0x08)
#define PORT_TX_LENGTH (BSP_CS8900_IO_BASE+0x0c)
#define PORT_ISQ (BSP_CS8900_IO_BASE+0x10)
#define PORT_PKTPG_PTR (BSP_CS8900_IO_BASE+0x14)
#define PORT_PKTPG_DATA (BSP_CS8900_IO_BASE+0x18)
#define PORT_PKTPG_DATA_1 (BSP_CS8900_IO_BASE+0x1c)
*/
/* PacketPage Offsets */
#define PKTPG_EISA_NUM 0x0000
#define PKTPG_PRODUCT_ID 0x0002
#define PKTPG_IO_BASE 0x0020
#define PKTPG_INT_NUM 0x0022
#define PKTPG_MEM_BASE 0x002C
#define PKTPG_EEPROM_CMD 0x0040
#define PKTPG_EEPROM_DATA 0x0042
#define PKTPG_RX_CFG 0x0102
#define PKTPG_RX_CTL 0x0104
#define PKTPG_TX_CFG 0x0106
#define PKTPG_BUF_CFG 0x010A
#define PKTPG_LINE_CTL 0x0112
#define PKTPG_SELF_CTL 0x0114
#define PKTPG_BUS_CTL 0x0116
#define PKTPG_TEST_CTL 0x0118
#define PKTPG_ISQ 0x0120
#define PKTPG_RX_EVENT 0x0124
#define PKTPG_TX_EVENT 0x0128
#define PKTPG_BUF_EVENT 0x012C
#define PKTPG_RX_MISS 0x0130
#define PKTPG_TX_COL 0x0132
#define PKTPG_LINE_ST 0x0134
#define PKTPG_SELF_ST 0x0136
#define PKTPG_BUS_ST 0x0138
#define PKTPG_TX_CMD 0x0144
#define PKTPG_TX_LENGTH 0x0146
#define PKTPG_IND_ADDR 0x0158
#define PKTPG_RX_STATUS 0x0400
#define PKTPG_RX_LENGTH 0x0402
#define PKTPG_RX_FRAME 0x0404
#define PKTPG_TX_FRAME 0x0A00
/* EEPROM Offsets */
#define EEPROM_IND_ADDR_H 0x001C
#define EEPROM_IND_ADDR_M 0x001D
#define EEPROM_IND_ADDR_L 0x001E
#define EEPROM_ISA_CFG 0x001F
#define EEPROM_MEM_BASE 0x0020
#define EEPROM_XMIT_CTL 0x0023
#define EEPROM_ADPTR_CFG 0x0024
/* Register Numbers */
#define REG_NUM_MASK 0x003F
#define REG_NUM_RX_EVENT 0x0004
#define REG_NUM_TX_EVENT 0x0008
#define REG_NUM_BUF_EVENT 0x000C
#define REG_NUM_RX_MISS 0x0010
#define REG_NUM_TX_COL 0x0012
/* Self Control Register */
#define SELF_CTL_RESET 0x0040
#define SELF_CTL_HC1E 0x2000
#define SELF_CTL_HCB1 0x8000
/* Self Status Register */
#define SELF_ST_INIT_DONE 0x0080
#define SELF_ST_SI_BUSY 0x0100
#define SELF_ST_EEP_PRES 0x0200
#define SELF_ST_EEP_OK 0x0400
#define SELF_ST_EL_PRES 0x0800
/* EEPROM Command Register */
#define EEPROM_CMD_READ 0x0200
#define EEPROM_CMD_ELSEL 0x0400
/* Bus Control Register */
#define BUS_CTL_USE_SA 0x0200
#define BUS_CTL_MEM_MODE 0x0400
#define BUS_CTL_IOCHRDY 0x1000
#define BUS_CTL_int_ENBL 0x8000
/* Bus Status Register */
#define BUS_ST_TX_BID_ERR 0x0080
#define BUS_ST_RDY4TXNOW 0x0100
/* @jla added for rdy4tx interrupt*/
/* Buf Event Register */
#define BUF_EVENT_RDY4TX 0x0100
/* Line Control Register */
#define LINE_CTL_RX_ON 0x0040
#define LINE_CTL_TX_ON 0x0080
#define LINE_CTL_AUI_ONLY 0x0100
#define LINE_CTL_10BASET 0x0000
/* Test Control Register */
#define TEST_CTL_DIS_LT 0x0080
#define TEST_CTL_ENDEC_LP 0x0200
#define TEST_CTL_AUI_LOOP 0x0400
#define TEST_CTL_DIS_BKOFF 0x0800
#define TEST_CTL_FDX 0x4000
/* Receiver Configuration Register */
#define RX_CFG_SKIP 0x0040
#define RX_CFG_RX_OK_IE 0x0100
#define RX_CFG_CRC_ERR_IE 0x1000
#define RX_CFG_RUNT_IE 0x2000
#define RX_CFG_X_DATA_IE 0x4000
/* Receiver Event Register */
#define RX_EVENT_RX_OK 0x0100
#define RX_EVENT_IND_ADDR 0x0400
#define RX_EVENT_BCAST 0x0800
#define RX_EVENT_CRC_ERR 0x1000
#define RX_EVENT_RUNT 0x2000
#define RX_EVENT_X_DATA 0x4000
/* Receiver Control Register */
#define RX_CTL_RX_OK_A 0x0100
#define RX_CTL_MCAST_A 0x0200
#define RX_CTL_IND_A 0x0400
#define RX_CTL_BCAST_A 0x0800
#define RX_CTL_CRC_ERR_A 0x1000
#define RX_CTL_RUNT_A 0x2000
#define RX_CTL_X_DATA_A 0x4000
/* Transmit Configuration Register */
#define TX_CFG_LOSS_CRS_IE 0x0040
#define TX_CFG_SQE_ERR_IE 0x0080
#define TX_CFG_TX_OK_IE 0x0100
#define TX_CFG_OUT_WIN_IE 0x0200
#define TX_CFG_JABBER_IE 0x0400
#define TX_CFG_16_COLL_IE 0x8000
#define TX_CFG_ALL_IE 0x8FC0
/* Transmit Event Register */
#define TX_EVENT_TX_OK 0x0100
#define TX_EVENT_OUT_WIN 0x0200
#define TX_EVENT_JABBER 0x0400
#define TX_EVENT_16_COLL 0x1000
/* Transmit Command Register */
#define TX_CMD_START_5 0x0000
#define TX_CMD_START_381 0x0080
#define TX_CMD_START_1021 0x0040
#define TX_CMD_START_ALL 0x00C0
#define TX_CMD_FORCE 0x0100
#define TX_CMD_ONE_COLL 0x0200
#define TX_CMD_NO_CRC 0x1000
#define TX_CMD_NO_PAD 0x2000
/* Buffer Configuration Register */
#define BUF_CFG_SW_int 0x0040
#define BUF_CFG_RDY4TX_IE 0x0100
#define BUF_CFG_TX_UNDR_IE 0x0200
/* ISA Configuration from EEPROM */
#define ISA_CFG_IRQ_MASK 0x000F
#define ISA_CFG_USE_SA 0x0080
#define ISA_CFG_IOCHRDY 0x0100
#define ISA_CFG_MEM_MODE 0x8000
/* Memory Base from EEPROM */
#define MEM_BASE_MASK 0xFFF0
/* Adpater Configuration from EEPROM */
#define ADPTR_CFG_MEDIA 0x0060
#define ADPTR_CFG_10BASET 0x0020
#define ADPTR_CFG_AUI 0x0040
#define ADPTR_CFG_10BASE2 0x0060
#define ADPTR_CFG_DCDC_POL 0x0080
/* Transmission Control from EEPROM */
#define XMIT_CTL_FDX 0x8000
/***************************************************************************/
/* 杨天池，增加的S3C2410寄存器 2003.11.2 */
/***************************************************************************/
#define BIT_EINT9 0x00000200
#define BIT_EINT8_23 (0x1<<5)
#define rSRCPND (*(volatile unsigned *)0x90a00000) //Interrupt request status
#define rINTMSK (*(volatile unsigned *)0x90a00008) //Interrupt mask control
#define rINTPND (*(volatile unsigned *)0x90a00010) //Interrupt request status
#define rEINTPEND (*(volatile unsigned *)0x916000a8) //External interrupt pending
#define rEXTINT1 (*(volatile unsigned *)0x9160008c) //External interrupt control register 1
#define rEINTMASK (*(volatile unsigned *)0x916000a4) //External interrupt mask
#define rGPGCON (*(volatile unsigned *)0x91600060) //Port G control
#define rGPGDAT (*(volatile unsigned *)0x91600064) //Port G data
#define rGPGUP (*(volatile unsigned *)0x91600068) //Pull-up control G
#define ClearPending(bit) {\
rSRCPND = bit;\
rINTPND = bit;\
rINTPND;\
}
/***************************************************************************/
/* 杨天池，结束的S3C2410寄存器 2003.11.2 */
/***************************************************************************/
/************************************************************************************/
STATUS CS8900A_Init(DV_DEVICE_ENTRY *device);
STATUS CS8900A_Close(NU_DEVICE *device);
STATUS CS8900A_Recv_Packet (DV_DEVICE_ENTRY *device,unsigned short RxEvent);
void CS8900A_Set_Address (uint8 *ether_addr, DV_DEVICE_ENTRY *device);
STATUS CS8900A_Get_Address (uint8 *ether_addr);
STATUS CS8900A_Open (uint8 *, DV_DEVICE_ENTRY *);
STATUS CS8900A_Xmit_Packet (DV_DEVICE_ENTRY *device, NET_BUFFER *buf_ptr);
STATUS CS8900A_Chip_Read( int16 io_addr, NET_BUFFER *buf_ptr, unsigned short *pFrame);
int CS8900A_Chip_Write(int16 io_addr, NET_BUFFER *buf_ptr);
void CS8900A_Recv_HISR (void);
void CS8900A_Transmit (void);
void CS8900A_LISR (long);
unsigned long CS8900A_VerifyChip(void);
unsigned long CS8900A_Reset(DV_DEVICE_ENTRY * device);
void CS8900A_Delay(void);
STATUS CS8900A_Ioctl(DV_DEVICE_ENTRY *dev, int option, DV_REQ *d_req);
void CS8900A_Update_Hash_Table(DV_DEVICE_ENTRY *device, int index);
uint32 CS8900A_Calculate_Hash(uint8 *multi_addr);
STATUS CS8900A_Set_RXCFG(DV_DEVICE_ENTRY *device);
int recv_intr_handle(DV_DEVICE_ENTRY *device);
void send_intr_handle(DV_DEVICE_ENTRY *device,uint8 int_status);
void CS8900A_BufferEvent(void);
STATUS CS8900A_Buffer_Packet (DV_DEVICE_ENTRY *device, NET_BUFFER *buf_ptr);
int CS8900A_Buffer_Write(int16 io_addr, NET_BUFFER *buf_ptr);
//unsigned int ioread16(unsigned int addr);
//void iowrite16(unsigned int addr,unsigned int data);
#endif
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