readme.txt

cypress fx2 firmware代码示例

This directory contains 8051 firmware for the Cypress Semiconductor EZ-USB FX2 
chip.

The purpose of this code is to demonstrate how the cpu can source an OUT packet 
in EZUSB FX2 Slave FIFO applications...

It configures FX2 as follows:
01).  EP2 512 4x BULK OUT - 8-bit async MANUAL mode
02).  EP6 512 4x BULK IN - 8-bit async AUTO mode
03).  FIFO strobes and flags are all active low
04).  FLAGA/B/C - indexed via FIFOADR[1:0] pins
05).  FX2 can't signal zerolen OUT token to the ext. master (in AUTO mode)


Hardware Pins (strap for initial condition):
============================================
PORTB (fifo data)
SLOE        GND
SLRD        VCC (through a 10k ohm resistor)
SLWR        VCC (through a 10k ohm resistor)
PKTEND      VCC (through a 10k ohm resistor)
FIFOADR0    GND
FIFOADR1    GND
FLAGB (full flag)
FLAGC (empty flag)

Chapter 9 of the EZUSB FX2 TRM explains the Slave FIFOs...

.....from "the user":
01).  Initially strap pins as outlined above..
02).  Setup Logic Analyzer to examine the pins outlined above...
03).  Download "srcout_s.hex"
04).  Issue "Get String"
05).  Issue "Get Pipes"
06).  Issue "Get Conf"
07).  Issue "Get Dev"
12).  Trigger Logic Analyzer on SLRD going low
10).  Issue BulkTrans EP2 OUT LEN -> 1 HEX BYTES -> 1
09).  Issue 0xBA VendReg 64 IN
10).  Issue BulkTrans EP2 OUT LEN -> 1 HEX BYTES -> 2
09).  Issue 0xBA VendReg 64 IN
10).  Issue BulkTrans EP2 OUT LEN -> 1 HEX BYTES -> 3
09).  Issue 0xBA VendReg 64 IN
10).  Issue BulkTrans EP2 OUT LEN -> 1 HEX BYTES -> 4
09).  Issue 0xBA VendReg 64 IN
12).  Trigger Logic Analyzer on SLRD going low (if applicable)
00).  Strobe SLRD (VCC-GND-VCC)
00).  Strobe SLRD (VCC-GND-VCC)
00).  Strobe SLRD (VCC-GND-VCC)
00).  Strobe SLRD (VCC-GND-VCC)
17).  Examine Logic Analyzer output      
      - should look similar to "SRCO_S01.TIF"
12).  Trigger Logic Analyzer on SLRD going low (if applicable)
09).  Issue 0xC2 VendReg 64 IN
00).  Strobe SLRD (VCC-GND-VCC)
17).  Examine Logic Analyzer output      
      - should look similar to "SRCO_S02.TIF"
      
NOTE: Manually providing a "strobe" to SLRD via a jumper may prove to not be
      a viable solution...  It may produce erroneous results.
      
      This example works significantly better with an external master...

The "srcout_s.hex" file loads into internal memory.
...issue "build -i" at the command prompt...

This example is for illustrative purpose(s)... You'll need a Logic Analyzer tied
to the DK 2x10 protoboard expansion headers (mapped for HP Logic Analyzer Pods)...