readme.txt

cypress fx2 firmware代码示例

The purpose of this code is to demonstrate how the cpu can source an OUT packet in EZUSB FX2 GPIF 
applications.

Chapter 10 of the EZUSB FX2 TRM explains the General Programmable Interface (GPIF).
This example configures FX2 as follows:
01). EP2 512 4x BULK OUT - 8-bit async MANUAL mode
02). EP6 512 4x BULK IN - 8-bit async MANUAL mode 

from "the user"
01). Initially strap:
- RDY0 to GND
- RDY1 to VCC (through a 10k ohm resistor)
02). Setup Logic Analyzer (similar to *.TIF files)
03). Download "gpiftool.hex"
04). Issue "Get String"
05). Issue "Get Pipes"
06). Issue "Get Conf"
07). Issue "Get Dev"
08). Trigger Logic Analyzer on CTL1 going low
09). Issue 0xC0 VendReg 64 IN
10). BulkTrans EP2 OUT 512 data
11). Examine Logic Analyzer output - should look similar to "SRCO_M01.TIF"
12). Trigger Logic Analyzer on CTL1 going low
13). Issue 0xC2 VendReg 64 IN
14). Examine Logic Analyzer output - should look similar to "SRCO_M02.TIF"
15). Trigger Logic Analyzer on CTL1 going low
16). BulkTrans EP2 OUT 512 data
17). Examine Logic Analyzer output - should look similar to "SRCO_M03.TIF"