📄 mul_two.v
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//==========================================================
// Latest Version: 2007-01-29
// Author: spoonylad
// Discription: parallel/parallel multiplier
//==========================================================
module MUL_TWO
( // input
clk, // system clock
rst, // system reset
mul_1, // multiplier 1
mul_2, // multiplier 2
// output
result // result of the multiplier
);
//----------------------------
// input
//----------------------------
input clk;
input rst;
input [3:0] mul_1;
input [3:0] mul_2;
//----------------------------
// output
//----------------------------
output [7:0] result;
//----------------------------
// reg
//----------------------------
reg [3:0] buff_mul_1;
reg [3:0] buff_mul_2;
reg [3:0] buff_x_0;
reg [3:0] buff_x_1;
reg [3:0] buff_x_2;
reg [3:0] buff_x_3;
reg [5:0] buff_s_1_10;
reg [5:0] buff_s_1_32;
reg [7:0] result;
//----------------------------
// wire
//----------------------------
wire [3:0] x_0;
wire [3:0] x_1;
wire [3:0] x_2;
wire [3:0] x_3;
wire [5:0] s_1_10;
wire [5:0] s_1_32;
wire [7:0] s_2;
//----------------------------
// receive multiplier 1 and multiplier 2
//----------------------------
always @ ( posedge clk or posedge rst )
begin
if ( rst )
begin
buff_mul_1 <= 4'd0;
buff_mul_2 <= 4'd0;
end
else
begin
buff_mul_1 <= mul_1;
buff_mul_2 <= mul_2;
end
end
//----------------------------
// calculate part product
//----------------------------
assign x_0 = buff_mul_2[0]? buff_mul_1:4'd0;
assign x_1 = buff_mul_2[1]? buff_mul_1:4'd0;
assign x_2 = buff_mul_2[2]? buff_mul_1:4'd0;
assign x_3 = buff_mul_2[3]? buff_mul_1:4'd0;
//----------------------------
// store part product
//----------------------------
always @ ( posedge clk or posedge rst )
begin
if ( rst )
begin
buff_x_0 <= 4'd0;
buff_x_1 <= 4'd0;
buff_x_2 <= 4'd0;
buff_x_3 <= 4'd0;
end
else
begin
buff_x_0 <= x_0;
buff_x_1 <= x_1;
buff_x_2 <= x_2;
buff_x_3 <= x_3;
end
end
//----------------------------
// calculate part sum
//----------------------------
assign s_1_10 = { 1'b0, buff_x_1, 1'b0 } + { 2'b00, buff_x_0 };
assign s_1_32 = { 1'b0, buff_x_3, 1'b0 } + { 2'b00, buff_x_2 };
//----------------------------
// store part sum
//----------------------------
always @ ( posedge clk or posedge rst )
begin
if ( rst )
begin
buff_s_1_10 <= 6'd0;
buff_s_1_32 <= 6'd0;
end
else
begin
buff_s_1_10 <= s_1_10;
buff_s_1_32 <= s_1_32;
end
end
//----------------------------
// calculate final sum
//----------------------------
assign s_2 = { buff_s_1_32, 2'b00 } + { 2'b00, buff_s_1_10 };
//----------------------------
// put the final sum out
//----------------------------
always @ ( posedge clk or posedge rst )
begin
if ( rst )
result <= 8'd0;
else
result <= s_2;
end
endmodule
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