📄 ti_cc_spi.c
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#include "include.h"
#include "myinlcude.h"
// Delay function. # of CPU cycles delayed is similar to "cycles". Specifically,
// it's ((cycles-15) % 6) + 15. Not exact, but gives a sense of the real-time
// delay. Also, if MCLK ~1MHz, "cycles" is similar to # of useconds delayed.
void TI_CC_Wait(unsigned int cycles)
{
while(cycles>15) // 15 cycles consumed by overhead
cycles = cycles - 6; // 6 cycles consumed each iteration
}
void TI_CC_SPIWriteReg(char addr, char value)
{
int temp;
enCS();
//CS enable
while (soReady); // Wait for CCxxxx ready
temp=SPIRXBUF; // Clear flag from first dummy byte
SPITXBUF = addr<<8; // Send address
while (!SPIRXIFG); // Wait for TX to finish
temp=SPIRXBUF; // Clear flag from first dummy byte
SPITXBUF = value<<8; // Send value
while (!SPIRXIFG);
disCS();//CS disable
}
void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
char i;
int temp;
enCS(); // CS enable
while (soReady);
temp=SPIRXBUF; // Wait for CCxxxx ready
SPITXBUF = (addr | TI_CCxxx0_WRITE_BURST)<<8; // Send address
while (!SPITXIFG);
temp=SPIRXBUF; // Wait for TX to finish
for (i = 0; i < count; i++)
{
SPITXBUF = buffer[i]<<8; // Send data
while (!SPITXIFG);
temp=SPIRXBUF; // Wait for TX to finish
}
disCS(); // CS disable
}
char TI_CC_SPIReadReg(char addr)
{
char x;
int temp;
enCS(); // CS enable
while (soReady);
temp=SPIRXBUF; // Wait for CCxxxx ready
SPITXBUF = (addr | TI_CCxxx0_READ_SINGLE)<<8; // Send address
while (!SPIRXIFG); // Wait for TX to finish
temp=SPIRXBUF; // Clear flag set during last write
SPITXBUF = 0<<8;
while (!SPIRXIFG); // Dummy write so we can read data // Wait for RX to finish
x = SPIRXBUF; // Read data
disCS(); // CS disable
return x;
}
void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
unsigned int i;
int temp;
enCS(); // CS enable
while (soReady); // Wait for CCxxxx ready
temp=SPIRXBUF;
// Clear flag
SPITXBUF = (addr | TI_CCxxx0_READ_BURST)<<8; // Send address
while (!SPITXIFG);
temp=SPIRXBUF; // Wait for TXBUF ready
SPITXBUF = 0<<8; // Dummy write to read 1st data byte
while (!SPIRXIFG); // Wait for end of addr byte TX // Wait for end of 1st data byte TX
for (i = 0; i < (count-1); i++)
{
buffer[i] = SPIRXBUF;
SPITXBUF = 0<<8;
while (!SPIRXIFG);
}
buffer[count-1] = SPIRXBUF;
disCS(); // CS disable
}
// For status/strobe addresses, the BURST bit selects between status registers
// and command strobes.
char TI_CC_SPIReadStatus(char addr)
{
char x;
int temp;
enCS(); // CS enable
while (soReady); // Wait for CCxxxx ready
temp=SPIRXBUF; // Clear flag set during last write
SPITXBUF = (addr | TI_CCxxx0_READ_BURST)<<8; // Send address
while (!SPIRXIFG); // Wait for TX to finish
temp=SPIRXBUF; // Clear flag set during last write
SPITXBUF = 0<<8; // Dummy write so we can read data
while (!SPIRXIFG); // Wait for RX to finish
x = SPIRXBUF; // Read data
disCS(); // CS disable
return x;
}
void TI_CC_SPIStrobe(char strobe)
{
int temp;
enCS(); // CS enable
while (soReady); // Wait for CCxxxx ready
temp=SPIRXBUF; // Clear flag
SPITXBUF = strobe<<8; // Send strobe
// Strobe addr is now being TX'ed
while (!SPIRXIFG); // Wait for end of addr TX
disCS(); // CS disable
}
void TI_CC_PowerupResetCCxxxx(void)
{
int temp;
disCS();
TI_CC_Wait(30);
enCS();
TI_CC_Wait(30);
disCS();
TI_CC_Wait(45);
enCS(); // CS enable
while (soReady);
// Wait for CCxxxx ready
SPITXBUF = TI_CCxxx0_SRES<<8; // Send strobe
// Strobe addr is now being TX'ed
temp=SPIRXBUF; // Clear flag
while (!SPIRXIFG);
// Wait for end of addr TX
while (soReady);
disCS(); // CS disable
}
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