ss.def

RISC处理器仿真分析程序。可以用于研究通用RISC处理器的指令和架构设计。在linux下编译

	"slti",			"t,s,i",
	IntALU,			F_ICOMP,
	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA,
	SET_GPR(RT, (GPR(RS) < IMM) ? 1 : 0))
DEFINST(SLTU, 			0x5d,
	"sltu", 		"d,s,t",
	IntALU, 		F_ICOMP,
	DGPR(RD), DNA,		DGPR(RS), DGPR(RT), DNA,
	SET_GPR(RD, (((unsigned)GPR(RS)) < ((unsigned)GPR(RT))) ? 1 : 0))
DEFINST(SLTIU,			0x5e,
	"sltiu",		"t,s,i",
	IntALU,			F_ICOMP,
	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA,
	SET_GPR(RT, ((unsigned)GPR(RS) < (unsigned)IMM) ? 1 : 0))


/*
 * Floating Point ALU operations
 */

DEFINST(FADD_S,			0x70,
	"add.s",		"D,S,T",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA,
	/* FIXME: check precedences here */
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 SET_FPR_F(FD, FPR_F(FS) + FPR_F(FT))))
DEFINST(FADD_D,			0x71,
	"add.d",		"D,S,T",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA,
	/* FIXME: check precedences here */
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 SET_FPR_D(FD, FPR_D(FS) + FPR_D(FT))))
DEFINST(FSUB_S,			0x72,
	"sub.s",		"D,S,T",
	FloatADD, 		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA,
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 SET_FPR_F(FD, FPR_F(FS) - FPR_F(FT))))
DEFINST(FSUB_D,			0x73,
	"sub.d",		"D,S,T",
	FloatADD, 		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA,
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 SET_FPR_D(FD, FPR_D(FS) - FPR_D(FT))))
DEFINST(FMUL_S,			0x74,
	"mul.s",		"D,S,T",
	FloatMULT, 		F_FCOMP|F_LONGLAT,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA,
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 SET_FPR_F(FD, FPR_F(FS) * FPR_F(FT))))
DEFINST(FMUL_D, 		0x75,
	"mul.d",		"D,S,T",
	FloatMULT, 		F_FCOMP|F_LONGLAT,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA,
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 SET_FPR_D(FD, FPR_D(FS) * FPR_D(FT))))
DEFINST(FDIV_S,			0x76,
	"div.s",		"D,S,T",
	FloatDIV,		F_FCOMP|F_LONGLAT,
	DFPR_F(FD), DNA,	DFPR_F(FS), DFPR_F(FT), DNA,
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 (DIV0(FPR_F(FT)), SET_FPR_F(FD, FDIV(FPR_F(FS), FPR_F(FT))))))
DEFINST(FDIV_D,			0x77,
	"div.d",		"D,S,T",
	FloatDIV,		F_FCOMP|F_LONGLAT,
	DFPR_D(FD), DNA,	DFPR_D(FS), DFPR_D(FT), DNA,
	(FPALIGN(FD), FPALIGN(FS), FPALIGN(FT),
	 (DIV0(FPR_D(FT)), SET_FPR_D(FD, FDIV(FPR_D(FS), FPR_D(FT))))))
DEFINST(FABS_S,			0x78,
	"abs.s",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_F(FD, fabs((double)FPR_F(FS)))))
DEFINST(FABS_D,			0x79,
	"abs.d",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_D(FD, fabs(FPR_D(FS)))))
DEFINST(FMOV_S,			0x7a,
	"mov.s",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_F(FD, FPR_F(FS))))
DEFINST(FMOV_D,			0x7b,
	"mov.d",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_D(FD, FPR_D(FS))))
DEFINST(FNEG_S,			0x7c,
	"neg.s",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_F(FD, -FPR_F(FS))))
DEFINST(FNEG_D,			0x7d,
	"neg.d",		"D,S",
	FloatADD,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_D(FD, -FPR_D(FS))))

DEFINST(CVT_S_D,		0x80, 
	"cvt.s.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_D(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_F(FD, (float)FPR_D(FS))))
DEFINST(CVT_S_W,		0x81,
	"cvt.s.w", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_F(FD), DNA,	DFPR_L(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_F(FD, (float)FPR_L(FS))))
DEFINST(CVT_D_S,		0x82,
	"cvt.d.s",		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_F(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_D(FD, (double)FPR_F(FS))))
DEFINST(CVT_D_W,		0x83,
	"cvt.d.w",		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_D(FD), DNA,	DFPR_L(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_D(FD, (double)FPR_L(FS))))
DEFINST(CVT_W_S,		0x84,
	"cvt.w.s", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_F(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_L(FD, FINT(FPR_F(FS)))))
DEFINST(CVT_W_D,		0x85,
	"cvt.w.d", 		"D,S",
	FloatCVT,		F_FCOMP,
	DFPR_L(FD), DNA,	DFPR_D(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_L(FD, FINT(FPR_D(FS)))))

DEFINST(C_EQ_S,			0x90,
	"c.eq.s", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_F(FS), DFPR_F(FT), DNA,
	(FPALIGN(FS), FPALIGN(FT), SET_FCC(FPR_F(FS) == FPR_F(FT))))
DEFINST(C_EQ_D,			0x91,
	"c.eq.d", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_D(FS), DFPR_D(FT), DNA,
	(FPALIGN(FS), FPALIGN(FT), SET_FCC(FPR_D(FS) == FPR_D(FT))))
DEFINST(C_LT_S,			0x92,
	"c.lt.s", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_F(FS), DFPR_F(FT), DNA,
	(FPALIGN(FS), FPALIGN(FT), SET_FCC(FPR_F(FS) < FPR_F(FT))))
DEFINST(C_LT_D,			0x93,
	"c.lt.d", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_D(FS), DFPR_D(FT), DNA,
	(FPALIGN(FS), FPALIGN(FT), SET_FCC(FPR_D(FS) < FPR_D(FT))))
DEFINST(C_LE_S,			0x94,
	"c.le.s", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_F(FS), DFPR_F(FT), DNA,
	(FPALIGN(FS), FPALIGN(FT), SET_FCC(FPR_F(FS) <= FPR_F(FT))))
DEFINST(C_LE_D,			0x95,
	"c.le.d", 		"S,T",
	FloatCMP,		F_FCOMP,
	DFCC, DNA,		DFPR_D(FS), DFPR_D(FT), DNA,
	(FPALIGN(FS), FPALIGN(FT), SET_FCC(FPR_D(FS) <= FPR_D(FT))))

DEFINST(FSQRT_S,		0x96,
	"sqrt.s",		"D,S",
	FloatSQRT,		F_FCOMP|F_LONGLAT,
	DFPR_F(FD), DNA,	DFPR_F(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_F(FD, sqrt((double)FPR_F(FS)))))
DEFINST(FSQRT_D,		0x97,
	"sqrt.d",		"D,S",
	FloatSQRT,		F_FCOMP|F_LONGLAT,
	DFPR_D(FD), DNA,	DFPR_D(FS), DNA, DNA,
	(FPALIGN(FD), FPALIGN(FS), SET_FPR_D(FD, sqrt(FPR_D(FS)))))


/*
 * miscellaneous
 */

DEFINST(SYSCALL, 		0xa0,
	"syscall", 		"",
	NA, 			F_TRAP,
	DNA, DNA,		DNA, DNA, DNA,
	SYSCALL(inst))
DEFINST(BREAK,			0xa1,
	"break",		"B",
	NA,			F_TRAP,
	DNA, DNA,		DNA, DNA, DNA,
	/* NOTE: these are decoded speculatively, as they occur in integer
	   divide sequences, however, they should NEVER be executed under
	   non-exception conditions */
	/* abort() */(void) 0)
DEFINST(LUI, 			0xa2,
	"lui",			"t,U",
	IntALU,			F_ICOMP,
	DGPR(RT), DNA, 		DNA, DNA, DNA,
	SET_GPR(RT, UIMM << 16))

DEFINST(MFC1,	 		0xa3,
	"mfc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DGPR(RT), DNA,		DFPR_L(FS), DNA, DNA,
	SET_GPR(RT, FPR_L(FS)))
DEFINST(DMFC1, 			0xa7,
	"dmfc1",		"t,S",
	IntALU,			F_ICOMP,
	DGPR_D(RT), DNA, 	DFPR_D(FS), DNA, DNA,
	(INTALIGN(RT), FPALIGN(FS),
	 SET_GPR(RT, FPR_L(FS)), SET_GPR((RT)+1, FPR_L((FS)+1))))
DEFINST(CFC1, 			0xa4,
	"cfc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DNA, DNA,		DNA, DNA, DNA,
	/* FIXME: is this needed */((void) 0))
DEFINST(MTC1, 			0xa5,
	"mtc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DFPR_L(FS), DNA,	DGPR(RT), DNA, DNA,
	SET_FPR_L(FS, GPR(RT)))
DEFINST(DMTC1,	 		0xa8,
	"dmtc1",		"t,S",
	IntALU,			F_ICOMP,
	DFPR_D(FS), DNA,	DGPR_D(RT), DNA, DNA,
	(FPALIGN(FS), INTALIGN(RT),
	 SET_FPR_L(FS, GPR(RT)), SET_FPR_L((FS)+1, GPR((RT)+1))))
DEFINST(CTC1, 			0xa6,
	"ctc1", 		"t,S",
	IntALU, 		F_ICOMP,
	DNA, DNA,		DNA, DNA, DNA,
	/* FIXME: is this needed */((void) 0))

#ifdef IMPL

/*
 * non-expression instruction implementations
 */

/*
 * rd <- [rt] >> SHAMT
 */
static void
InstSRA(SS_INST_TYPE inst)
{
  unsigned int i;

  /* Although SRA could be implemented with the >> operator in most
     machines, there are other machines that perform a logical
     right shift with the >> operator. */
  if (GPR(RT) & 020000000000) {
    SET_GPR(RD, GPR(RT));
    for (i = 0; i < SHAMT; i++) {
      SET_GPR(RD, (GPR(RD) >> 1) | 020000000000);
    }
  }
  else {
    SET_GPR(RD, GPR(RT) >> SHAMT);
  }
}

/*
 * rd <- [rt] >> [5 LSBs of rs])
 */
static void
InstSRAV(SS_INST_TYPE inst)
{
  unsigned int i;
  unsigned int shamt = GPR(RS) & 037;

  if (GPR(RT) & 020000000000) {
    SET_GPR(RD, GPR(RT));
    for (i = 0; i < shamt; i++) {
      SET_GPR(RD, (GPR(RD) >> 1) | 020000000000);
    }
  }
  else {
    SET_GPR(RD, GPR(RT) >> shamt);
  }
}

/*
 * HI,LO <- [rs] * [rt], integer product of [rs] & [rt] to HI/LO
 */
static void
InstMULT(SS_INST_TYPE inst)
{
  int sign1, sign2;
  int i, op1, op2;

  sign1 = sign2 = 0;
  SET_HI(0);
  SET_LO(0);
  op1 = GPR(RS);
  op2 = GPR(RT);

  /* For multiplication, treat -ve numbers as +ve numbers by
     converting 2's complement -ve numbers to ordinary notation */
  if (op1 & 020000000000) {
    sign1 = 1;
    op1 = (~op1) + 1;
  }
  if (op2 & 020000000000) {
    sign2 = 1;
    op2 = (~op2) + 1;
  }
  if (op1 & 020000000000)
    SET_LO(op2);
  for (i = 0; i < 31; i++) {
    SET_HI(HI << 1);
    SET_HI(HI + extractl(LO, 31, 1));
    SET_LO(LO << 1);
    if ((extractl(op1, 30-i, 1)) == 1) {
      if (((unsigned)037777777777 - (unsigned)LO) < (unsigned)op2) {
	SET_HI(HI + 1);
      }
      SET_LO(LO + op2);
    }
  }

  /* Take 2's complement of the result if the result is negative */
  if (sign1 ^ sign2) {
    SET_LO(~LO);
    SET_HI(~HI);
    if ((unsigned)LO == 037777777777) {
      SET_HI(HI + 1);
    }
    SET_LO(LO + 1);
  }
}

/*
 * HI,LO <- [rs] * [rt], integer product of [rs] & [rt] to HI/LO
 */
static void
InstMULTU(SS_INST_TYPE inst)
{
  int i;

  SET_HI(0);
  SET_LO(0);
  if (GPR(RS) & 020000000000)
    SET_LO(GPR(RT));
  for (i = 0; i < 31; i++) {
    SET_HI(HI << 1);
    SET_HI(HI + extractl(LO, 31, 1));
    SET_LO(LO << 1);
    if ((extractl(GPR(RS), 30-i, 1)) == 1) {
      if (((unsigned)037777777777 - (unsigned)LO) < (unsigned)GPR(RT)) {
	SET_HI(HI + 1);
      }
      SET_LO(LO + GPR(RT));
    }
  }
}

#endif /* IMPL */