relax.cfg

来自「RISC处理器仿真分析程序。可以用于研究通用RISC处理器的指令和架构设计。在l」· CFG 代码 · 共 27 行

#
# relax.cfg	- relax resource restrictions, useful for debugging dependence
#		  related problems.
#

# no cache/TLB
-cache:dl1      none # l1 data cache config, i.e., {<config>|none}
-cache:dl2      none # l2 data cache config, i.e., {<config>|none}
-cache:il1      none # l1 inst cache config, i.e., {<config>|dl1|dl2|none}
-cache:il2      none # l2 instruction cache config, i.e., {<config>|dl2|none}
-tlb:itlb       none # instruction TLB config, i.e., {<config>|none}
-tlb:dtlb       none # data TLB config, i.e., {<config>|none}

# beacoup resources
-res:ialu       8 # total number of integer ALU's available
-res:imult      8 # total number of integer multiplier/dividers available
-res:memport    8 # total number of memory system ports available (to CPU)
-res:fpalu      8 # total number of floating point ALU's available
-res:fpmult     8 # total number of floating point multiplier/dividers available

-fetch:ifqsize  16 # instruction fetch queue size (in insts)
-decode:width   16 # instruction decode B/W (insts/cycle)
-issue:width    16 # instruction issue B/W (insts/cycle)
-ruu:size       128 # register update unit (RUU) size
-lsq:size       64 # load/store queue (LSQ) size