📄 ramtest.xa
字号:
$include xa-h3.equ
$include rm.equ
$list
sram equ 00h
; start code space:
org 0000h
dw $8f00, start
dw $8f00, BreakVec
dw $8f00, TraceVec
dw $8f00, StkOvfVec
dw $8f00, Div0Vec
dw $8f00, URetiVec
org $40
dw $8800, Trap0Vec
dw $8800, Trap1Vec
dw $8800, Trap2Vec
dw $8800, Trap3Vec
dw $8800, Trap4Vec
dw $8800, Trap5Vec
dw $8800, Trap6Vec
dw $8800, Trap7Vec
dw $8800, Trap8Vec
dw $8800, Trap9Vec
dw $8800, Trap10Vec
dw $8800, Trap11Vec
dw $8800, Trap12Vec
dw $8800, Trap13Vec
dw $8800, Trap14Vec
dw $8800, Trap15Vec
org $80
dw $9b00, ExtInt0Vec
dw $8a00, Timer0Vec
dw $8900, ExtInt1Vec
dw $8900, Timer1Vec
dw $8900, ExtInt2Vec
dw $a900, DMALVec
dw $b900, DMAHVec
org $A0
dw $a900, Uart0_1
dw $b900, Uart2_3
org $b0
dw $8900, HSWI0Vec
dw $8900, HSWI1Vec
dw $8900, HSWI2Vec
dw $8900, HSWI3Vec
org $100
dw $8100, SWI1Vec
dw $8200, SWI2Vec
dw $8300, SWI3Vec
dw $8400, SWI4Vec
dw $8500, SWI5Vec
dw $8600, SWI6Vec
dw $8700, SWI7Vec
;=======================================================================
; initialization code
;=======================================================================
; beginning of initialization code.
org 0200h ; offset for programming into otp xa or eprom's
BreakVec:
TraceVec:
StkOvfVec:
Div0Vec:
URetiVec:
jmp error
Trap0Vec:
Trap1Vec:
Trap2Vec:
Trap3Vec:
Trap4Vec:
Trap5Vec:
Trap6Vec:
Trap7Vec:
Trap8Vec:
Trap9Vec:
Trap10Vec:
Trap11Vec:
Trap12Vec:
Trap13Vec:
Trap14Vec:
Trap15Vec:
reti
;***********************************************************************
ExtInt0Vec:
reti
;***********************************************************************
Timer0Vec:
djnz.w cpu_count,t0_exit
mov.w cpu_count,#03e8h ; one second flash led
jbc run,t0_exit
setb run
t0_exit:
reti
;***********************************************************************
ExtInt1Vec:
Timer1Vec:
ExtInt2Vec:
reti
;***********************************************************************
DMALVec:
reti
;***********************************************************************
DMAHVec:
reti
;***********************************************************************
Uart0_1:
Uart2_3:
HSWI0Vec:
HSWI1Vec:
HSWI2Vec:
HSWI3Vec:
SWI1Vec:
SWI2Vec:
SWI3Vec:
SWI4Vec:
SWI5Vec:
SWI6Vec:
SWI7Vec:
reti
;***********************************************************************
start:
mov.b wdcon,#0 ; turn off watchdog timer
mov.b wfeed1,#a5h ; feed watchdog so new config takes effect
mov.b wfeed2,#5ah
;Set MMR base address = fff000h , and enable access to MMRs.
mov.b mrbh,#ffh
mov.b mrbl,#f1h
;Configure SSEL DS and ES SFRs.
mov.b ssel,#28h ;r3 r5 es point
mov.b ds,#00h
mov.b es,#ffh
;Set up bus timing registers
mov.b btrh,#51h ;btrh must be 51h
mov.b btrl,#40h ;btrl must be 40h
nop
nop
nop
nop
nop
nop
;Unlock memory bank configuration locks, in prep.
mov.w r5,#mbcl
mov.b [r5],#3ch
;Set up memory bank 0. CS0 attsched to 128k byte flash.
mov.w r5,#b0cfg
mov.b [r5+],#89h
mov.b [r5+],#00h
mov.b [r5],#10h
;Set up memory bank 1. CS1 attsched to 256k byte sram.
mov.w r5,#b1cfg
mov.b [r5+],#cah
mov.b [r5+],#sram
mov.b [r5],#48h
call ledblink
;Check SRAM Memory
call check_sram
call ledblink
call ledblink
;Initial Uart0
mov.w r5,#u0wr4
mov.b [r5],#0ch ;wr4[3,2] = 01 , 2 stop bit per character
mov.w r5,#u0wr1
mov.b [r5],#00h ;wr1 = 00 , all interrupt disable
mov.w r5,#u0wr3 ;wr3[7,6] = 11 , 8 rx bit/character
mov.b [r5],#c0h ;wr3[0] = 1 , enable receiver
mov.w r5,#u0wr5 ;wr5[6,5] = 11 , 8 tx bit/character
mov.b [r5],#60h ;wr5[3] = 1 , enable transmitter
mov.w r5,#u0wr14
mov.b [r5],#02 ;wr14[1] = 1 , Pclk
mov.w r5,#u0wr0 ;wr0[0] = 0 , 1 CLOCK
mov.b [r5],#00 ;wr0[1] = 0 , RTCLK0
mov.w r5,#u0wr12
mov.b [r5],#3fh ;wr13 wr12 = 831 with 32 MHz
mov.w r5,#u0wr13
mov.b [r5],#03h ; baud rate 9600
mov.w r5,#u0wr14
mov.b r4l,[r5]
or.b r4l,#01h
mov.b [r5],r4l ;wr14[0] = 1 , enable baudrate generator
mov.w r5,#u0wr11 ;wr11[6,5] = 10 , BRGOUT
mov.b [r5],#50h ;wr11[4,3] = 10 , BRGOUT
mov.w r5,#u0wr15
mov.b [r5],#05h ;wr15 = 00000101 , IE bit not enable
mov.w r5,#u0wr5 ;wr5[6,5] = 11 , 8 tx bit/character
mov.b r4l,[r5]
or.b r4l,#08h
mov.b [r5],r4l ;wr5[3] = 1 , enable transmitter
mov.w r5,#u0wr1 ;rx interrupt on all character
mov.b [r5],#10h ;tx interrupt enable
mov.w r5,#u0wr9
mov.b [r5],#08h ;master interrupt enable
mov.w r5,#u0wr3 ;wr3[7,6] = 11 , 8 rx bit/character
mov.b r4l,[r5]
or.b r4l,#01h
mov.b [r5],r4l ;wr3[0] = 1 , enable receiver
mov.w r5,#u0wr0
mov.b r4l,[r5]
or.b r4l,#10h
mov.b [r5],r4l ;reset interrupt
mov.w r5,#u0wr0
mov.b r4l,[r5]
or.b r4l,#10h
mov.b [r5],r4l ;reset interrupt
mov.w r5,#u0wr0
mov.b r4l,[r5]
or.b r4l,#30h
mov.b [r5],r4l ;error reset command
;Set up I/O Port.
mov.b p0cfga,#ffh
mov.b p0cfgb,#01h
setb p0.0
mov.w r5,#u0wr11
mov.b r4l,[r5]
or.b r4l,#02h
mov.b [r5],r4l
mov.w r5,#u2wr11
mov.b r4l,[r5]
and.b r4l,#fch
mov.b [r5],r4l
mov.b p1cfga,#ffh
mov.b p1cfgb,#00h
or.b rstsrc,#80h ;enable reset output
setb rst_ad
;; setb t0oe ;disable t0 output
mov.w r5,#u1wr11 ;p3.3 setup
mov.b r4l,[r5]
and.b r4l,#fch ;wr11[1,0] = 00 ,~brg1 off
mov.b [r5],r4l
setb t1oe ;disable t1 output
mov.w r5,#pmcr ;p3.6 setup
mov.w r4,[r5]
setb r4.4 ;pmcr[4] = 1
mov.w [r5],r4
mov.b p3cfga,#dch
mov.b p3cfgb,#67h
mov.b r3h,#250
call dlynms
mov.b r3h,#250
call dlynms
mov.b r3h,#250
call dlynms
mov.b r3h,#250
call dlynms
mov.b r3h,#250
call dlynms
mov.b r3h,#250
call dlynms
call ledblink
call ledblink
call ledblink
;; call initial_interrupt
mov.b tmod,#00h ;timer0 in auto-reload mode
mov.b tcon,#01h ;int0 falling edge trigger
mov.b ipa0,#abh ;t0 0ah int0 0bh
mov.b ipa2,#90h
mov.b ipa4,#99h
mov.b tl0,#c0h
mov.b th0,#e0h
mov.b rtl0,#c0h
mov.b rth0,#e0h
;; or.b swe,#0fh ;enable software interrupt 1,2,3,4
mov.b iel,#02h ;enable even interrupt T1 DMAL
mov.b ieh,#01h ;enable uart0 & uart1 intererupt
setb tr0
setb tr1
initial_value:
mov.w cpu_count,#03e8h; one second flash led
clr rx0_f
mov.b pswh,#a0h
mov.w r2,#rx0_buf_start
mov.w r7, #0100h ;stack point
mov.b pswh,#80h
setb ea ;enable interrupts
;
; ======= start main measurement and display loop ========
;
main:
jmp main
;
; =============== end main measurement =================
;
check_sram:
mov.b ds,#sram
mov.w r0,#0100h ;do'nt check iram
set_eram:
mov.w r1,#aaaah
mov.w [r0],r1
mov.w r1,[r0]
cmp.w r1,#aaaah
bne error
mov.w r1,#5555h
mov.w [r0],r1
mov.w r1,[r0]
cmp.w r1,#5555h
bne error
mov.w r1,#0000h
mov.w [r0],r1
add.w r0,#0002
bcc set_eram
mov.w r0,#0000h
add.b ds,#01
cmp.b ds,#sram+04
blt set_eram
mov.b ds,#00
ret
;***********************************************************************
error:
clr ea
call ledblink
jmp error
;***********************************************************************
dlynms:
call dly1ms ; delay n times 1 millisecond
djnz.b r3h,dlynms
ret
dly1ms: ; wait (498*4)+4 mach. cycles
mov.b r3l,#250 ; this equals approx. 1 ms at 24 mhz
xa_adjust_0000:
djnz.b r3l,$
mov.b r3l,#249
xa_adjust_0001:
djnz.b r3l,$
ret
;
; ledblink: blink the led
;
; entry: nothing
; calls: dlynms
; trashes: nothing(saves and restores r1,r3 )
; assumes: nothing
; exit: nothing
ledblink:
clr run
mov.b r3h,#250 ; delay here
call dlynms
mov.b r3h,#250
call dlynms
setb run
mov.b r3h,#250 ; delay here
call dlynms
mov.b r3h,#250
call dlynms
ret
;***********************************************************************
end
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