target.ref

Freescale mpc827x 系列CPU的VxWorks平台的BSP源代码。

    m8260Flash.c - flash memory driver
    m8260Sio.c - serial driver
    m8260IntrCtl.c - interrupt controller driver
    m8260Timer.c - timer driver
    motFccEnd.c - FCC Ethernet END driver
    miiLib.c - Media Independent Interface library
    mot82xxPci.c - On-chip PCI Bridge library/interrupt handler.

The BSP configures both SCC1 and SCC4 as UART devices.
SCC1 is used as a console device.
FCC1/2 are used as ethernet ports.

\sh Memory Maps

The memory map is described in the Motorola board documentation.  The
memory map is completely configurable by the bsp, however we have
kept the map as described.  However there is a remapping of the IMMR
(internal memory map register) provided.  During debugging it can be
desireable to leave the internal memory map as defined by the hard
reset configuration word.  This makes using a visionICE or visionPROBE
simpler because the emulator always knows where the internal map is.

The bsp defaults to leaving the memory map as defined by the hard
reset config word.  If you want to map it to the value as described in
the board manual, simply define IMMAP_REMAP in config.h.



The following table describes the ads8260 default memory map:
\ts


Start | Size | End | Access to
------------------------------
0x0000_0000 | 16MB | 0x03FF_FFFF | Soldered SDRAM 
0x0440_0000 | 1MB | 0x044F_FFFF | Unused
0x0450_0000 | 32KB | 0x0450_7FFF | Board Control and Status Registers
 | | | (BCSR0 through BCSR7 on PROTOTYPE revision)
0x0450_8000 |  | 0x045F_FFFF | Unused
0x0460_0000 | 32KB | 0x0460_7FFF | ATM (unsupported)
0x0460_8000 |  | 0x046F_FFFF | Unused
0x0470_0000 | 64KB | 0x0471_FFFF | MPC 8260 Internal Memory
 | | | (see MPC8260 PowerQUICC II User's Manual,
 | | | Chapter 3, Memory Map, and
 | | | Chapter 13, CPM Overview, for further details,
 | | | and see Parameter Ram below)
0x0472_0000 |  | 0xFCFF_FFFF | Unused
0xFF80_0000 | 8MB | 0xFFFF_FFFF | Flash SIMM
\te






The following table describes the default VxWorks macros which
are used to address memory
\ts


Macro Name | Macro Definition | Description
------------------------------
LOCAL_MEM_LOCAL_ADRS | 0x0000_0000 | Base of RAM
RAM_LOW_ADRS | LOCAL_MEM_LOCAL_ADRS + 0x0001_0000
 | VxWorks image loaded here. Stack grows down from this address.
RAM_HIGH_ADRS | LOCAL_MEM_LOCAL_ADRS + 0x00d0_0000
 | VxWorks bootrom loaded here.
LOCAL_MEM_SIZE | 0100_0000 | Default 16 MBytes of RAM
BCSR_BASE_ADRS | 0450_0000 | Default location of Board Control and Status Registers on PROTOTYPE rev
BCSRS_SIZE | 0001_0000 | 64 KBytes on PROTOTYPE rev
DEFAULT_IMM_ADRS | 0F00_0000 | Default location of MPC 8260 Internal Memory Map
DEFAULT_IMM_ADRS | 0470_0000 | Remapped location of MPC 8260 Internal Memory Map
IMM_SIZE | 0x20000 | 128K Internal Memory Map Size
ROM_BASE_ADRS | 0xFFF0_0000 | Base address of ROM on PROTOTYPE rev
ROM_TEXT_ADRS | ROM_BASE_ADRS + 0x100
 | Text must start after vector table
ROM_WARM_ADRS | ROM_TEXT_ADRS + 8
 | Warm Reboot Entry Address
ROM_SIZE | 0x0010_0000 | Default 1 MByte of ROM on PROTOTYPE rev (see ROM considerations)
\te


\sh Shared Memory
NA

\sh PCI Support


The support include PCI DMA and PCI Error Handling.
The standard mapping for PCI is described in config.h of this BSP and uses
outbound translation to access. This means PCI space usage is configurable by
the user in config.h.
INCLUDE_PCI_DMA intialises the interrupt and handlers for PCI Bridge DMA
INCLUDE_PCI_ERROR_HANDLING intialises the interrupt and handlers for PCI
Bridge Error handling interrupts and a show routine (pciErrorShow) detailing
which errors have occured and how many.


\sh Interrupts


The following table describes the relationship between the interrupt
number, interrupt vector, and the interrupt bit position in the SIU
Interrupt Mask Register (SIMR_H and SIMR_L). Also described is the
mask to use to enable all interrupts of a higher priority. See m8260IntrCtl.c
for usage. This is compatible with previous 8260 parts. 
\ts
Default |  |  |  | Mask to Enable|
Interrupt | Interrupt | Interrupt | SIMR | Higher Priority Interrupts | Interrupt
Priority | Number | Vector | Mask | SIMR_H | SIMR_L | Source
 |  |  |  |  |  | HIGHEST PRIORITY
1 | 16 | 0x10 | H 0x00000004 | 0000_0000 | 0000_0000 | TMCNT
2 | 16 | 0x10 | H 0x00000004 | 0000_0000 | 0000_0000 | TMCNT
3 | 17 | 0x11 | H 0x00000002 | 0000_0004 | 0000_0000 | PIT
4 | 18 | 0x12 | H 0x00000001 | 0000_0006 | 0000_0000 | PCI
5 | 19 | 0x13 | H 0x00004000 | 0000_0006 | 0000_0000 | IRQ1
6 | 27 | 0x20 | L 0x80000000 | 0000_4006 | 0000_0000 | FCC1
7 | 28 | 0x21 | L 0x40000000 | 0000_4006 | 8000_0000 | FCC2
8 | 29 | 0x22 | L 0x20000000 | 0000_4006 | C000_0000 | FCC3
9 | inactive
10 | unused
11 | 31 | 0x24 | L 0x08000000 | 0000_4006 | E000_0000 | MCC1
12 | 32 | 0x25 | L 0x04000000 | 0000_4006 | E800_0000 | MCC2
13 | inactive
14 | inactive
15 | 20 | 0x13 | H 0x00002000 | 0000_4006 | EC00_0000 | IRQ2
16 | 21 | 0x14 | H 0x00001000 | 0000_6006 | EC00_0000 | IRQ3
17 | 22 | 0x15 | H 0x00000800 | 0000_7006 | EC00_0000 | IRQ4
18 | 23 | 0x16 | H 0x00000400 | 0000_7806 | EC00_0000 | IRQ5
19 | unused
20 | 35 | 0x28 | L 0x00800000 | 0000_7C06 | EC00_0000 | SCC1
21 | 36 | 0x29 | L 0x00400000 | 0000_7C06 | EC80_0000 | SCC2
22 | 37 | 0x2A | L 0x00200000 | 0000_7C06 | ECC0_0000 | SCC3
23 | 38 | 0x2B | L 0x00100000 | 0000_7C06 | ECE0_0000 | SCC4
24 | inactive
25 | inactive
26 | inactive
27 | inactive
28 | unused
29 | 40 | 0x30 | H 0x00010000 | 0000_7C06 | ECF0_0000 | PC15
30 | 12 | 0x0C | L 0x00000010 | 0001_7C06 | ECF0_0000 | Timer 1
31 | 41 | 0x31 | H 0x00020000 | 0001_7C06 | ECF0_0010 | PC14
32 | unused
33 | 42 | 0x32 | H 0x00040000 | 0003_7C06 | ECF0_0010 | PC13
34 | 10 | 0x0A | L 0x00000040 | 0007_7C06 | ECF0_0010 | SDMA Bus Error
35 | 6 | 0x06 | L 0x00000400 | 0007_7C06 | ECF0_0050 | IDMA1
36 | unused
37 | 43 | 0x33 | H 0x00080000 | 0007_7C06 | ECF0_0450 | PC12
38 | 44 | 0x34 | H 0x00100000 | 000F_7C06 | ECF0_0450 | PC11
39 | 7 | 0x07 | L 0x00000200 | 001F_7C06 | ECF0_0450 | IDMA2
40 | 13 | 0x0D | L 0x00000008 | 001F_7C06 | ECF0_0650 | Timer 2
41 | 45 | 0x35 | H 0x00200000 | 001F_7C06 | ECF0_0658 | PC10
42 | unused
43 | unused
44 | 3 | 0x03 | L 0x00002000 | 003F_7C06 | ECF0_0658 | RISC Timer Table
45 | 1 | 0x01 | L 0x00008000 | 003F_7C06 | ECF0_2658 | I2C
46 | unused
47 | 46 | 0x36 | H 0x00400000 | 003F_7C06 | ECF0_A658 | PC9
48 | 47 | 0x37 | H 0x00800000 | 007F_7C06 | ECF0_A658 | PC8
49 | 24 | 0x18 | H 0x00000200 | 00FF_7C06 | ECF0_A658 | IRQ6
50 | 8 | 0x08 | L 0x00000100 | 00FF_7E06 | ECF0_A658 | IDMA3
51 | 25 | 0x19 | H 0x00000100 | 00FF_7E06 | ECF0_A758 | IRQ7
52 | 14 | 0x0E | L 0x00000004 | 00FF_7F06 | ECF0_A758 | Timer 3
53 | unused
54 | unused
55 | 48 | 0x38 | H 0x01000000 | 00FF_7F06 | ECF0_A75C | PC7
56 | 49 | 0x39 | H 0x02000000 | 01FF_7F06 | ECF0_A75C | PC6
57 | 50 | 0x3A | H 0x04000000 | 03FF_7F06 | ECF0_A75C | PC5
58 | 15 | 0x0F | L 0x00000002 | 07FF_7F06 | ECF0_A75C | Timer 4
59 | unused
60 | 51 | 0x3B | H 0x08000000 | 07FF_7F06 | ECF0_A75E | PC4
61 | unused
62 | 9 | 0x09 | L 0x00000080 | 0FFF_7F06 | ECF0_A75E | IDMA4
63 | 2 | 0x02 | L 0x00004000 | 0FFF_7F06 | ECF0_A7DE | SPI
64 | 52 | 0x3C | H 0x10000000 | 0FFF_7F06 | ECF0_E7DE | PC3
65 | 53 | 0x3D | H 0x20000000 | 1FFF_7F06 | ECF0_E7DE | PC2
66 | 4 | 0x04 | L 0x00001000 | 3FFF_7F06 | ECF0_E7DE | SMC1
67 | unused
68 | 5 | 0x05 | L 0x00000800 | 3FFF_7F06 | ECF0_F7DE | SMC2
69 | 54 | 0x3E | H 0x40000000 | 3FFF_7F06 | ECF0_FFDE | PC1
70 | 55 | 0x3F | H 0x80000000 | 7FFF_7F06 | ECF0_FFDE | PC0
71 | unused
72 | unused
73 | reserved
 |  |  |  |  |  | LOWEST PRIORITY

\te

\sh Serial Configuration
SCC1 and SCC4 are configured as UART devices with 8 data bits, 1 stop
bit, hardware handshaking, and parity disabled.

\sh SCSI Configuration
There is no SCSI interface on this board.

\sh Network Configuration
FCC1 and FCC2 is configured as an Ethernet port

\sh VME Access
NA

\sh PCI Access
PCI interface is available.

\sh Boot Devices
motfcc

\sh Boot Methods
Ethernet

SPECIAL CONSIDERATIONS
This section describes miscellaneous information that the user needs
to know about the BSP.

\sh Delivered Objects

\sh Make Targets
Bootrom_uncmp, vxWorks and vxWorks.st are delivered. All other
make targets are untested. For PROTOTYPE revision of board, bootrom
(compressed) is also tested.

\sh Special Routines
None

\sh Serial Connections
Most VxWorks BSPs do not use hardware handshaking in the serial
interface, and thus a simple 3 wire connection is commonly used.  The
MPC8260 ADS BSP does use hardware handshaking and this requires
a full 8 pin interface. Standard molded RS-232 cables have been shown
to work, possibly requiring a null modem adapter.

See also "Known Problems" below.

\sh Ethernet Address
The MPC82xx ADS boards do not have a unique Ethernet hardware
address assigned to each board.  A unique address is absolutely necessary if
the user wishes to connect the board to a network.  Thus, the user
must provide a suitable 6 byte Ethernet address for each board used
on a network. The MAC address is setup in the bootrom using the 'M' command.  
The user must change the last three bytes to three unique bytes
(i.e., bytes not used by any other Wind River board on your net).
Check with your system administrator if you do not know this information.
This means a new bootrom must programmed if this feature wasn't already 
implemented in the last bootrom image programmed and 'M' must be called for 
both FCC devices.

\sh Known Problems
vxWorks does not implement support of critical/machine check exceptions.

\sh SYSCLK Frequency
Most Motorola sample code and documentation refers to a default system clock
frequency of 100 MHz

BOARD LAYOUT
The diagram below shows jumpers and connectors relevant to
VxWorks configuration for ADS8272 PROTOTYPE revision of the board.

\bs
___________________________________________________________________________
|  	                   SW3/6/7 Reset/Power   SW5 - Modck              |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
| P23 - FETH 2 (FCC2)        P21 - COP/JTAG                               |
|                                                                         |
|                                                                         |
|                                                                         |
|                                         SW2 - PCI/Boot Source           |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
| P13 - Serial SCC1 & 4                                                   |
|       Top SCC1/RS232-1                                                  |
|       Bottom SCC4/RS232-2                                               |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
| P10 - FETH 1 (FCC1)                                                     |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                            -------------                        ________|
|     P4 - CPM expansion     |            |  P16 - SYS expansion  |
|____________________________|            |_______________________|
\be
    Key:
    X  vertical jumper installed
    :  vertical jumper absent
    -  horizontal jumper installed
    "  horizontal jumper absent
    0  switch off
    1  switch on
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    L  three-pin horizontal jumper, left jumper installed
    R  three-pin horizontal jumper, right jumper installed

SEE ALSO
\tb Tornado User's Guide: Getting Started, 
\tb VxWorks Programmer's Guide: Configuration, 
\tb VxWorks Programmer's Guide: Architecture Appendix 

BIBLIOGRAPHY

\tb MPC8272 Reference Manual 
\tb MPC8272ADS Board Manual 
\tb MPC8266ADS-PCI User's Manual
\tb MPC826x PowerQUICC II Errata 
\tb MPC8260 ADS User's Manual 
\tb MPC8260ADS User's Manual, for PILOT revision bd, 11/1999 
\tb PowerQUICC II User's Manual, rev. 0 
\tb MPC8260 PowerQUICC II User's Manual Errata, rev. 0 
\tb MPC8260 Design Checklist 
\tb PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors MPCFPE32B/AD 
\tb MPC603e & EC603e RISC Microprocessors User's Manual MPC603EUM/AD 
\tb VBUG PowerQUICC II Debugger 


WEB RESOURCES

Much of the Motorola documentation can be found on line. The following
URL was correct at the time of writing for semiconductor area. You'll have to search the documentation using processor name for specific documentation.

http://e-www.motorola.com/