syslib.c

Freescale mpc834x 的VxWorks平台的BSP源代码。

/* sysLib.c - Wind River SBC834x board system-dependent library */

/*
 * Copyright (c) 2005-2006 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/*
modification history
--------------------
01e,25aug06,dtr  WIND0061424 - CPU 1 errata causes intermittent crash.
                 WIND0061584 - default image doesn't boot
01d,08mar06,kds  Set optimal SCCR settings for TSEC/USB and SEC engine. Fix
                 PVR check. Add USB support.
01c,28oct05,mdo  SPR#114197 - protect against multiple defines for
                 INCLUDE_PCICFG_SHOW
01b,22jul05,j_b  remove FEI END support
01a,21jun05,j_b  adapted from ads834x (rev 01e); add NV RAM support
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

                        
INCLUDE FILES:

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include <vxWorks.h>
#include <vme.h>
#include <memLib.h>
#include <cacheLib.h>
#include <sysLib.h>
#include "config.h"
#include <string.h>
#include <intLib.h>
#include <logLib.h>
#include <stdio.h>
#include <taskLib.h>
#include <vxLib.h>
#include <tyLib.h>
#include <arch/ppc/mmu603Lib.h>
#include <arch/ppc/vxPpcLib.h>
#include <private/vmLibP.h>

#include <miiLib.h>
#ifdef INCLUDE_PCI
#    include <drv/pci/pciConfigLib.h>
#    include <drv/pci/pciIntLib.h>
#endif /* INCLUDE_PCI */

/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with caching and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT + _MMU_NUM_EXTRA_IBAT + _MMU_NUM_EXTRA_DBAT)] =
    {
    /* I BAT 0 */
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_8M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    /* use DBAT1 to map CPM DPRAM and internal registers into data space */
    /* NOTE! the internal space cannot be cached and should be guarded */
    ((CCSBAR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CCSBAR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 2 */

    ((0x80000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0x80000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
     _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 4 */

    ((0x90000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0x90000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
     _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /*
     * These entries are for the I/D BATs (4-7) on the MPC7455/755/834x/8272.
     * They should be defined in the following order.
     * IBAT4U,IBAT4L,IBAT5U,IBAT5L,IBAT6U,IBAT6L,IBAT7U,IBAT7L,
     * DBAT4U,DBAT4L,DBAT5U,DBAT5L,DBAT6U,DBAT6L,DBAT7U,DBAT7L,
     */

    /* I BAT 4 */

    ((LOCAL_MEM_LOCAL_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((LOCAL_MEM_LOCAL_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_MEM_COHERENT),


    /* I BAT 5 */

    0, 0,

    /* I BAT 6 */

    0, 0,

    /* I BAT 7 */

    0, 0,

    /* D BAT 4 */

    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_8M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 5 */

    0, 0,

    /* D BAT 6 */

    0, 0,

    /* D BAT 7 */

    0, 0


    };

/*
 * mmuPcpBatInitMPC7x5 initializes the standard 4 (0-3) I/D BATs &
 * the additional 4 (4-7) I/D BATs present on the MPC74[45]5 & MPC83xx.
 */

IMPORT void mmuPpcBatInitMPC7x5(UINT32 *pSysBatDesc); /* MPC7x5 and 83xx BAT Support */
IMPORT FUNCPTR _pSysBatInitFunc;

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, EEPROM, 
 * the MPC834x Internal Memory Map, and local FLASH RAM are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory      Page Table size
 * -------------------      ---------------
 *        8 Meg              64 K
 *       16 Meg             128 K
 *       32 Meg             256 K
 *       64 Meg             512 K
 *      128 Meg               1 Meg
 *  .               .
 *  .               .
 *  .               .
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {

    {
    /* Vector Table and Interrupt Stack */

    (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS,
    (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_GUARDED |
    VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_GUARDED |
    VM_STATE_CACHEABLE_NOT
    },

    {
    /* Vector Table and Interrupt Stack */

    (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS + RAM_LOW_ADRS,
    (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS + RAM_LOW_ADRS,
    LOCAL_MEM_SIZE - RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      |
    VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
    },

#ifdef INCLUDE_SECONDARY_DRAM
    {
    /* Vector Table and Interrupt Stack */

    (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS2,
    (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS2,
    LOCAL_MEM_SIZE2,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      |
    VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
    },
#endif

    {
    /* EEPROM */

    (VIRT_ADDR) EEPROM_BASE_ADRS,
    (PHYS_ADDR) EEPROM_BASE_ADRS,
    EEPROM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    }

    ,
    {
    /* MPC8349 Internal Memory Map */

    (VIRT_ADDR) CCSBAR,
    (PHYS_ADDR) CCSBAR,
    CCSBAR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    }

    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int   sysBus      = BUS;                /* system bus type (VME_BUS, etc) */
int   sysCpu      = CPU;                /* system CPU type (PPC8260) */
char *sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;   /* catastrophic message area */
int   sysProcNum;           /* processor number of this CPU */
int   sysFlags;             /* boot flags */
char  sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */
BOOL  sysVmeEnable = FALSE;     /* by default no VME */
UINT32   baudRateGenClk;

/* forward declarations */

uint32_t sysBaudClkFreq(void);
UINT32   sysClkFreqGet();

void   sysLedClkRoutine (int arg);
STATUS sysSwitchRead(int);

#ifdef INCLUDE_PCI
  STATUS sysPciSpecialCycle (int busNo, UINT32 message);
  STATUS sysPciConfigRead   (int busNo, int deviceNo, int funcNo,
                             int offset, int width, void * pData);
  STATUS sysPciConfigWrite  (int busNo, int deviceNo, int funcNo,
                             int offset, int width, ULONG data);

  void   sysPciConfigEnable (int);
  
  ULONG sysPciConfAddr = (PCI_CFG_ADR_REG | CCSBAR); /* PCI Configuration Addr */
  ULONG sysPciConfData = (PCI_CFG_DATA_REG | CCSBAR); /* PCI Configuration Data */


#  include <pci/pciIntLib.c>           /* PCI int support */
#  include <pci/pciConfigLib.c>        /* pci configuration library */

  /* use show routine */
#if (defined(INCLUDE_PCI_CFGSHOW) && !defined(PRJ_BUILD))
#    include <pci/pciConfigShow.c>     /* pci configuration show routines */
#endif /* (defined(INCLUDE_PCI_CFGSHOW) && !defined(PRJ_BUILD)) */

   /* use pci auto config */

#  include <pci/pciAutoConfigLib.c>    /* automatic PCI configuration */
#  include "sysBusPci.c"               /* pciAutoConfig BSP support file */
#  include "mot83xxPci.c"
 
#ifdef INCLUDE_GEI8254X_END
LOCAL int   sysPci1SysNum  = PCI_1_BUS;
#ifdef  INCLUDE_SECONDARY_PCI
LOCAL int   sysPci2SysNum  = PCI_2_BUS;
#endif /* INCLUDE_SECONDARY_PCI */
#endif /* INCLUDE_GEI8254X_END */

#endif /* INCLUDE_PCI */

#include "sysDuart.c"
#include <intrCtl/quiccIntrCtl.c>

#include <timer/quiccTimer.c>

#if (NV_RAM_SIZE == NONE)
#  include <mem/nullNvRam.c>
#else
#  include "eeprom.c"
#  include <mem/byteNvRam.c>
#endif

#ifdef INCLUDE_SYSLED
#  include "sysLed.c"
#endif /* INCLUDE_SYSLED */

/* defines */

#define ZERO    0
#define SYS_MODEL_8349  "Wind River SBC8349"
#define SYS_MODEL_8349E "Wind River SBC8349E"
#define SYS_MODEL_8347T  "Wind River SBC8347 TBGA"
#define SYS_MODEL_8347ET  "Wind River SBC8347E TBGA"
#define SYS_MODEL_8347P  "Wind River SBC8347 PBGA"
#define SYS_MODEL_8347EP  "Wind River SBC8347E PBGA"
#define SYS_MODEL_8343E "Wind River SBC8343E"
#define SYS_MODEL_8343 "Wind River SBC8343"


#define SYS_MODEL_UNKNOWN "Not an E300 core - device unknown"

/* Set ACR to park on PCI bus */
#define M83XX_ACR_PARKM_PCI 0x1

/* needed to enable timer base */
#ifdef INCLUDE_PCI
#  define      M8260_DPPC_MASK    0x0C000000 /* bits 4 and 5 */
#  define      M8260_DPPC_VALUE   0x0C000000 /* bits (4,5) should be (1,0) */
#else
#  define      M8260_DPPC_MASK    0x0C000000 /* bits 4 and 5 */
#  define      M8260_DPPC_VALUE   0x08000000 /* bits (4,5) should be (1,0) */
#endif /*INCLUDE_PCI */


/* network support */
#ifdef INCLUDE_END
#  include "sysNet.c"

#  ifdef INCLUDE_MOT_TSEC_END
#    include "sysMotTsecEnd.c"
#  endif /* INCLUDE_MOT_TSEC_END */

#  ifdef INCLUDE_GEI_END
#    include "sysGei82543End.c"
#  endif

#endif /* INCLUDE_END */

#ifdef PCI_BRIDGE_READ_ERRATA_WORKAROUND
  UCHAR   sysInByte(ULONG port)
      {
      return(pciBridgeRegisterReadByte(port));
      }

  USHORT  sysInWord(ULONG port)
      {
      return(pciBridgeRegisterReadWord(port));
      }

  ULONG   sysInLong(ULONG port)
      {
      return(pciBridgeRegisterReadLong(port));
      }
#endif /*PCI_BRIDGE_READ_ERRATA_WORKAROUND */

/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    char * model;
    if ((vxPvrGet() & 0xffff0000) == 0x80830000)
    {
    UINT32 temp;
    temp=vxSvrGet();
    switch(temp & 0xffff0000)
        {
        case 0x80500000:
        model = SYS_MODEL_8349E;
        break;
        case 0x80510000:
        model = SYS_MODEL_8349;
        break;
        case 0x80520000: