target.ref

Freescale mpc834x 的VxWorks平台的BSP源代码。

a value of 0 configures COM1 and 1 configures COM2.

\sh SCSI Configuration
There is no SCSI interface on this board.

\sh Network Configuration

The supported boot devices are:
    mottsec - Three speed 10/100/1000BaseT Ethernet controller
        - unit 0 is channel TSEC1, unit 1 is TSEC2
    gei - Intel Pro1000 Ethernet PCI adaptor with a 8254x controller,
	          when the PCI bus is enabled
        - unit 0 is the only unit available, since there is only 1 PCI slot

The "mottsec" boot device corresponds to the on-board TSEC network interfaces.
The "gei" boot device is for use with PCI Ethernet adapters with an Intel 8254x
Gigabit Ethernet controller.  The "gei" network interface can only be used when
the PCI bus is supported and INCLUDE_GEI_END is defined in config.h.  See the
"PCI Access" and "PCI Support" sections for more information about PCI bus
support.

\sh Setting the Ethernet Address

The SBC834x boards are assigned unique Ethernet hardware or MAC addresses at the
factory.  These MAC addresses should be listed on label affixed to the board.
A unique 6 byte address is absolutely necessary if the board will be connected
to a network. The first 3 bytes are a Wind River-specific prefix. The last 3
bytes are unique.

The MAC addresses can be set by writing them directly to NVRAM using the
'M' command from the boot ROM prompt.  This option allows only the last three
bytes to be changed.  To use this option, open a console window and reset the
hardware.  When the bootrom banner appears and the countdown starts, press any
key to get the "[VxWorks Boot]:" prompt.  Type 'M' and follow the instructions.

The BSP supports storage of 2 MAC addresses in NVRAM, one for each on-board
Ethernet device.  Ethernet Addresses are assigned and stored by END device
number:
\ts
END device # | Boot Device | Physical Channel
---------------------------------------------
0 | mottsec0 | TSEC1
1 | mottsec1 | TSEC2
\te

\sh VME Access
NA

\sh PCI Access

Support is included for the MPC8349E/7E PCI controller that enables access to
a single 66Mhz, 64-bit PCI slot.  However, the BSP is configured to disable PCI
access by default due to MPC8349E/7E Errata.  This errata causes:
    - PCI Autoconfiguration to fail; and
    - An unpopulated PCI slot accessed via a configuration cycle will cause
      the board to hang.

PCI interrupts are configured using IRQ0 as a maskable external interrupt.

PCI support is enabled by defining INCLUDE_PCI in config.h.

The Intel PRO/1000 T Ethernet PCI card (GEI) was tested in the PCI slot.

Note that the default reset configuration sets the default PCI clock frequency
to 66 MHz.  If a 33 MHz PCI card is installed in the PCI slot, the reset
configuration word may need to be changed.

PCI addresses are accessed via a 1 to 1 memory map with LOCAL and PCI memory
space:
\cs
CPU Addr                                         PCI Addr
PCI_LOCAL_MEM_BUS     --------0x00000000-------- PCI_MSTR_MEM_BUS
                      -                        -
                      -                        -
PCI_LOCAL_MEM_BUS +   --------0x10000000-------- PCI_MSTR_MEM_BUS +
PCI_LOCAL_MEM_SIZE    -                        - PCI_MSTR_MEM_SIZE
                      -                        -
                      -                        -
                      -                        -
                      -                        -
CPU_PCI_MEM_ADRS      --------0x80000000-------- PCI_MEM_ADRS
                      -                        -
                      -                        -
CPU_PCI_MEMIO_ADRS    --------0x90000000-------- PCI_MEMIO_ADRS
                      -                        -
                      -                        -
CPU_PCI_IO_ADRS       --------0xA0000000-------- PCI_IO_BASE
                      -                        -
                      -                        -
CPU_PCI_IO_ADRS +     --------0xB0000000-------- PCI_IO_BASE +
CPU_PCI_IO_SIZE       -                        - PCI_IO_SIZE
                      -                        -
                      -                        -
                      -                        -
                      -------------------------- 4GBytes
\ce

\sh TrueFFS support

This BSP supports TrueFFS for the on-board Flash. To include TrueFFS support in
the BSP, the INCLUDE_TFFS macro must be defined in config.h.  TrueFFS support is
not built into the default BSP.  In sysTffs.c, TrueFFS is configured to use the
upper 4MB of Flash, protecting the Hard Reset Configuration Word and bootrom
image from being overwritten.

\sh Delivered Objects
The following images are delivered with the wrSbcPowerQuiccII BSP:
    bootrom_uncmp
    bootrom_uncmp.hex
    bootrom
    bootrom.hex
    vxWorks
    vxWorks.st


\sh Make Targets
Only bootrom, bootrom_uncmp, vxWorks and vxWorks.st have been tested.

\sh Special Routines
None


SPECIAL CONSIDERATIONS
This section describes miscellaneous information that the user needs
to know about the BSP.

\sh Serial Connections
Most VxWorks BSPs do not use hardware handshaking in the serial
interface, and thus a simple 3 wire connection is commonly used.

\sh Ethernet Addresses
Use the bootrom 'M' command to initialize the MAC addresses for the TSEC
devices. The MAC addresses are provided on a label behind the JTAG port.
If the MAC addresses are not initialized, the following message may result:
\cs
        Attaching interface lo0 done
        muxDevLoad failed for device entry 0!
        muxDevLoad failed for device entry 1!
        Failed to attach to device (null) Can't load boot file.
\ce

\sh Hard Reset Configuration Words
If a Wind River ICE or Probe cannot enter background mode (BKM) when attempting
to connect to the board, the Hardware Reset Configuration Words (HRCWs) in Flash
memory may have been corrupted.  To get into BKM, set the HRCWs in the processor
by entering "cf rcw 0x04230000 0xf460a000" at the >ERR> prompt.  Once in BKM,
the HRCWs can be re-programmed into Flash using the SBC834x Reset Configuration
Word Image (i.e., SBC8349_rstconf_clkin66_core400_ddr266.bin) provided with the
board.

\sh Known Problems

CPU Errata

Due to MPC8349E Family Errata, the following limitations should be noted:
    - Bootrom doesn't always execute after power-on reset or when the reset button
      is pressed (this was fixed with rev 1.1 CPUs);
    - Machine Check Exception is not supported and will cause the board to hang if
      triggered; and
    - If INCLUDE_PCI is defined, an access to an unpopulated PCI slot (via
      a configuration cycle) will cause the board to hang. (this was fixed with
      rev 1.1 CPUs).

Hardware Limitations

The following limitations of the Wind River SBC834x board should be noted:
    - To avoid mechanical interferences with the Plexiglas enclosure, the PCI slot
      should only be used in the stand-alone configuration;
    - Note that the default reset configuration sets the default PCI clock frequency
      to 66 MHz.  If a 33 MHz PCI card is installed in the PCI slot, the reset
      configuration word may need to be changed; and
    - I2C interface circuitry is untested.

TSEC Link Speed Changes

The TSEC driver does not properly sense changes in link speed.  Therefore, an
increase or decrease in the speed of the link (ex., 100bps -> 1000bps or
1000bps -> 100bps) will cause a loss of communication with a TSEC connection.
The TSEC driver will need to be re-started (ex., reboot vxWorks) in order for
the TSEC to communicate at the new link speed.

BOARD LAYOUT

See the "Wind River SBC8349E/47E Engineering Reference Guide" for drawings of
the board.

BIBLIOGRAPHY

\tb Wind River SBC8349E/47E Engineering Reference Guide, ERG-00328-001
\tb Wind River SBC8349E/47E Reference Design Schematics, SCH-00328-001
\tb MPC8349 PowerQUICC II Pro Integrated Host Processor Reference Manual, MPC8349ERM
\tb MPC8349E PowerQUICC II Pro Family Device Errata, MPC8349ECE
\tb e300 PowerPC Core Reference Maunual, e300coreRM
\tb PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors MPCFPE32B/AD

WEB RESOURCES

Much of the Freescale documentation can be found on line. The following
URL was correct at the time of writing for semiconductor area. Please search
the documentation using processor name for specific documentation.

http://www.freescale.com/