target.ref

Freescale mpc834x 的VxWorks平台的BSP源代码。

\" wrSbc834x/target.ref - Wind River SBC834x target specific documentation
\"
\" Copyright 2005-2006 Wind River Systems, Inc.
\"
\" modification history
\" --------------------
\" 01b,15mar06,kds  Updated supported features USB and PCI autoconfig.
\" 01a,01jun05,kds  Modified from ads834x (rev 01a).
\"
\TITLE wrSbc834x - Wind River SBC834x

NAME
`Wind River SBC834x'

INTRODUCTION
This reference entry provides board-specific information necessary to run
VxWorks for the wrSbc834x BSP.

\sh Board Jumper & Switch Settings

The board's default jumper and switch configurations should have been
set correctly by the factory to allow vxWorks to run.  See the
"Wind River SBC8349E/47E Engineering Reference Guide" for details.

\sh Boot ROM
Images 'bootrom.hex' and 'bootrom_uncmp.hex' are provided with this BSP and
are configured to a ROM base address of 0x0. When programming the bootrom to the
FLASH, an offset of 0xFFF00100 (the location of the reset exception) needs to be
given.  The bootrom images provided are configured to execute from the Flash ROM
on a Wind River SBC8349E/47E target using an onboard 10/100/1000BaseT TSEC
Ethernet port as the default boot device and the COM1 (top) serial port as the
default console device.

\sh Programming a bootrom image using Wind River Workbench:

Connect a terminal or terminal emulator to the board using the top 9 pin mini
connector.  The terminal parameters should be set to 9600 baud, 8 bit data,
no parity, 1 stop bit.

\ml
\m 1.
Establish communications between Workbench and a Wind River ICE or Probe by
following the instructions given in the associated Workbench guide
"Wind River ICE for Wind River Workbench Hardware Reference Guide" or
"Wind River Probe for Wind River Workbench Hardware Reference Guide".

Select the appropriate processor (MPC8347 or MPC8349) when defining a launch
configuration.

When communications have been successfully established, the Background Mode
(>BKM>) prompt should appear in the OCD Command Shell view.

Following the instructions in the "Wind River Workbench On-Chip Debugging Guide"
section, "Programming a VxWorks Boot ROM into Flash Memory":

\m 2.
Enter the board's register file, provided with the board
(ex., WRS_SBC8349_PCT00328001.reg or WRS_SBC8347_PCT00328002.reg),
in the 'Playback File' field of the 'Command View Settings' dialog.

\m 3.
Under the 'Configuration View' tab of the 'Flash Programming View', select the
Flash device configuration for AMD 28F640Jx, (4096 x 16), 1 Device.

Enter 0xFFF00000 in the 'Base' field of the 'Flash Bank Addresses' section and
the list of sectors will be displayed.

Enter 0 in the 'Start' field of the 'RAM Workspace' section.

Select sectors starting at 0xFFF00000 to the end of the sector list.  These
define the area of Flash to erase and program.

\m 4.
A bootrom.hex image will need to be converted into a .bin file to program Flash.
Under the 'File View' tab of the 'Flash Programming View', select the
'Convert file' button.

Find the bootrom.hex file to convert and click the 'Convert and Add File' button
in the File Conversion Utility dialog.  The default 'Start' and 'End' addresses
of 0x0 and 0xFFFFFFFF are correct for this file.

\m 5.
Now that bootrom.bin has been added to the 'File View' tab, change the
'Start Address' field to 0xFFF00100.  Remember to click on the 'Enabled'
checkbox to enable the file.

\m 6.
Verify that the data in the 'Flash Settings' and 'Erase Sectors' area of the
'Programming View' tab are set to the correct values and click the
'Erase/Program' button.

\m 7.
Reset the board or set the program counter at 0xFFF00100 in the Workbench
On-Chip Debugger and execute the bootrom image.
\me


FEATURES

\sh Supported Features

    MPC8349E/47E PowerQUICC II Pro Processors, including
    - Instruction and Data caches
    - MMU
    - Interrupt Controller
    - PowerPC decrementer timer, used to implement a System Clock.
    - UART1 as the default console channel
    - UART2
    - General Purpose Timers 1 and 2 cascaded as a 32-bit Auxiliary clock
    - General Purpose Timers 3 and 4 cascaded as a 32-bit Timestamp clock
    - TSEC1 & 2 as Ethernet devices supporting 10BaseT/100BaseT/1000BaseT protocol
    256MB DDR SDRAM
    128MB Local Bus SDRAM
    8MB Intel 28F640J3A StrataFlash (16-bit)
    8KB EEPROM/Non-volatile memory as boot parameter and MAC address storage
    PCI Bus Interface (with auto configuration)
    USB Host
    Security Engine (SEC) - verified with test code but not using IPSEC.
    7 segment display
    User DIP switch bank


\sh Unsupported Features

    Inter-IC Interfaces (I2C)
    Serial Peripheral Interface (SPI)
    DMA Controller/Messaging Unit

HARDWARE DETAILS
This section documents the details of the device drivers and board
hardware elements.

\sh Devices
The device drivers included are:

    ns16550Sio.c - serial driver
    quiccIntrCtl.c - interrupt controller driver
    quiccTimer.c - timer driver
    eeprom.c - EEPROM access routines
    motTsecEnd.c - TSEC Ethernet END driver
    mot83xxPci.c - PowerQUICC II Pro PCI Bridge driver
    cfiscs.c - Flash memory access routines for TFFS

\sh Memory Maps

The memory map is described in the SBC8349 Engineering Reference Guide. The
memory map is completely configurable by the bsp, however we have
kept the map as described.

The following table describes the SBC8349 default memory map:
\ts

Start | Size | End | Access to
------------------------------
0x0000_0000 | 256MB | 0x0FFF_FFFF | DDR SDRAM
0x1000_0000 | 64MB  | 0x17FF_FFFF | LBC SDRAM
0x8000_0000 | 512MB | 0x9fff_FFFF | PCI1
0xF800_0000 | 8KB   | 0xF800_1FFF | EEPROM
0xFF80_0000 | 8MB   | 0xFFFF_FFFF | Flash
\te

\sh NVRAM Support

This BSP implements Nonvolatile RAM via an EEPROM device.  There are a few
macros associated with this device. The macros are located in the config.h file
and are:
\cs
    #define INCLUDE_EEPROM_LOCKING
    #define SMART_EEPROM_WRITE
\ce
The INCLUDE_EEPROM_LOCKING parameter is typically #define'd.  When defined, the
EEPROM is software locked between accesses.

The SMART_EEPROM_WRITE parameter is typically #define'd. When defined, the
EEPROM write code first checks to see if a cell is the desired value.  If the
memory location already contains the desired value, the write is skipped.  This
was implemented to increase the life of the EEPROM device.

\sh Shared Memory
NA

\sh Interrupts

The SBC8349E/7E internal interrupt sources are assigned their default priorities
as provided in the "MPC8349 PowerQUICC II Pro Integrated Host Processor
Reference Manual".  The external interrupt sources are:
\ts
External Interrupt | Interrupt Source
-------------------------------------
IRQ0 | PCI INT A
IRQ1 | PCI INT B
IRQ2 | PCI INT C
IRQ3 | PCI INT D
IRQ4 | Gigabit PHY A
IRQ5 | Gigabit PHY B
IRQ6 | Not Connected
IRQ7 | Not Connected
\te

\sh Serial Configuration

UART1 and UART2 are configured as serial devices with 8 data bits, 1 stop bit,
hardware handshaking, and parity disabled.  UART1 is the default console
channel, accessed by the COM1 port.  UART2 is accessible by the COM2 port.
The default console port is determined by CONSOLE_TTY in config.h, where