syslib.c

Freescale MPC85xx BSP (8555/8541)。绝对可用的。

/* sysLib.c - Freescale cds85xx board system-dependent library */

/*
 * Copyright (c) 2003-2005 Wind River Systems, Inc.
 *
 * The right to copy, distribute or otherwise make use of this software
 * may be licensed only pursuant to the terms of an applicable Wind River
 * license agreement. No license to Wind River intellectual property rights
 * is granted herein. All rights not licensed by Wind River are reserved
 * by Wind River.
 */

#include "copyright_wrs.h"

/*
modification history
--------------------
01v,24mar05,mdo  Documentation fixes for apigen
01u,22mar05,dtr  Include Tsec configlette .
01t,22nov04,jln  set ASTME bit for cache
01s,21nov04,jln  fixed compiler warning
01r,02sep04,jln  modified from ads85xx/01q
01q,30jul04,dtr  Fixing sysMsDelay, added saveExcMsg.
01p,22jul04,dtr  Disable ICACHE after boot up for initialisation.
01o,31mar04,dtr  Some minor mods. Install parity handler. 
                 Branch prediction support.
01n,20nov03,dtr  Setting HID1 ABE bit by default .
01m,03nov03,dtr  Minor fixes..
01l,27oct03,dtr  Use GNU_TOOL instead of __GCC__.
01k,21oct03,dtr  Remove EUMBAR read/write.
01j,17oct03,dtr  Modifying Pvr lkup.
01i,29sep03,dtr  Set default aux clock setting if included.
01h,09sep03,dtr  Clear L2 control register prior to Enable.
01g,20aug03,dtr  Adding in TSEC configlette file. 
                 Adding new FCC2 End driver support.
                 Test for bootrom then initialise static TLB entries.
                 Adding dynamic config of L1 cache.
01f,04aug03,dtr  Adding in support for LBC SDRAM.
01e,29jul03,dtr  Removing CCSBAR magic number,support for MMU 'off' and
                 support for SNOOP when MMU 'off'.
01d,24jul03,mil  Added storing of flash params.
01c,19jun03,mil  Changed ROM TLB entry to writable, added SCC and FCC.
01b,07jan03,dtr  Adding TLB static table entries.
01a,13oct02,dtr  More complete file for further development.
*/

/*
DESCRIPTION
This library provides board-specific routines for ADS85XX.

INCLUDE FILES:

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/mmuE500Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "private/vmLibP.h"
#include "miiLib.h"

#ifdef INCLUDE_PCI
    #include "drv/pci/pciConfigLib.h"
    #include "drv/pci/pciIntLib.h"
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_CPM
    #include "m8560CpmIntrCtl.h"
#endif

/* globals */

TLB_ENTRY_DESC sysStaticTlbDesc [] =
{
    /* effAddr,  Unused,  realAddr, ts | size | attributes | permissions */

    /* TLB #0.  Flash */

    /* needed be first entry here */
    { FLASH1_BASE_ADRS, 0x0, FLASH1_BASE_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M |
        _MMU_TLB_IPROT | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | 
        _MMU_TLB_ATTR_G
    },
    /* LOCAL MEMORY needed be second entry here  - 
     * one TLB would be 256MB so use to get required 512MB 
     */
    { 0x00000000, 0x0, 0x00000000, _MMU_TLB_TS_0 | _MMU_TLB_SZ_256M | 
        _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_M | 
        CAM_DRAM_CACHE_MODE | _MMU_TLB_IPROT
    },
    { 0x10000000, 0x0, 0x10000000, _MMU_TLB_TS_0 | _MMU_TLB_SZ_256M | 
        _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_M | 
        CAM_DRAM_CACHE_MODE | _MMU_TLB_IPROT
    }, 

#ifdef INCLUDE_LBC_SDRAM
    /* needed be second entry here */
    { LOCAL_MEM_LOCAL_ADRS2, 0x0, LOCAL_MEM_LOCAL_ADRS2, _MMU_TLB_TS_0 | 
        _MMU_TLB_SZ_64M | _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | 
        CAM_DRAM_CACHE_MODE | _MMU_TLB_ATTR_M | _MMU_TLB_IPROT
    },
#endif /* LBC_SDRAM */

    { CCSBAR, 0x0, CCSBAR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | 
        _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W
    }, 
    { CCSBAR, 0x0, CCSBAR, _MMU_TLB_TS_1 | _MMU_TLB_SZ_16M | 
        _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W
    }

#ifdef INCLUDE_L2_SRAM
    ,
    { L2SRAM_ADDR, 0x0, L2SRAM_ADDR, _MMU_TLB_TS_0 | _MMU_TLB_SZ_256K | 
        _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | 
        _MMU_TLB_ATTR_G
    }

#endif /* INCLUDE_L2_SRAM */

    /* 16 MB of LBC CS 3 area */
    , {
        LBC_CS3_LOCAL_ADRS, 0x0, LBC_CS3_LOCAL_ADRS,
        _MMU_TLB_TS_0   | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT |
        _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_ATTR_M
    }

    /* Assume PCI space contiguous and within 256MB */
#ifdef INCLUDE_PCI
    ,
    { PCI_MEM_ADRS, 0x0, PCI_MEM_ADRS, _MMU_TLB_TS_0 | PCI_MMU_TLB_SZ | 
        _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W
    }
#ifdef INCLUDE_CDS85XX_SECONDARY_PCI
    ,
    { PCI_MEM_ADRS2, 0x0, PCI_MEM_ADRS2, _MMU_TLB_TS_0 |  PCI_MMU_TLB_SZ | 
        _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W
    }
#endif /* INCLUDE_CDS85XX_SECONDARY_PCI */

#endif  /* INCLUDE_PCI */

};

int sysStaticTlbDescNumEnt = NELEMENTS (sysStaticTlbDesc);


/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, the Board Control and
 * Status registers, the MPC8260 Internal Memory Map, and local FLASH RAM are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 */
PHYS_MEM_DESC sysPhysMemDesc [] =
{

    {
        /* Vector Table and Interrupt Stack */
        /* Must be sysPhysMemDesc [0] to allow adjustment in sysHwInit() */

        (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS,
        (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS,
        LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | TLB_CACHE_MODE | VM_STATE_MEM_COHERENCY
    }
#ifdef INCLUDE_LBC_SDRAM
    ,
    {
        /* Must be sysPhysMemDesc [2] to allow adjustment in sysHwInit() */
        (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS2,
        (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS2,
        LOCAL_MEM_SIZE2,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY ,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | TLB_CACHE_MODE | VM_STATE_MEM_COHERENCY
    }
#endif /* INCLUDE_LBC_SDRAM */

#ifdef INCLUDE_L2_SRAM
    ,
    {
        (VIRT_ADDR) L2SRAM_ADDR,
        (PHYS_ADDR) L2SRAM_ADDR,
        256 * 1024,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
#endif

#ifdef INCLUDE_LBC_CS3
    ,{
        (VIRT_ADDR) LBC_CS3_LOCAL_ADRS,
        (PHYS_ADDR) LBC_CS3_LOCAL_ADRS,
        16 * 0x100000,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
#endif /* INCLUDE_LBC_CS3 */

#ifdef INCLUDE_PCI
    ,
    {
        (VIRT_ADDR) PCI_MEM_ADRS,
        (PHYS_ADDR) PCI_MEM_ADRS,
        PCI_MEM_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
    ,
    {
        (VIRT_ADDR) PCI_MEMIO_ADRS,
        (PHYS_ADDR) PCI_MEMIO_ADRS,
        PCI_MEMIO_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
    ,
    {
        (VIRT_ADDR) PCI_IO_ADRS,
        (PHYS_ADDR) PCI_IO_ADRS,
        PCI_IO_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }

#ifdef INCLUDE_CDS85XX_SECONDARY_PCI
    ,
    {
        (VIRT_ADDR) PCI_MEM_ADRS2,
        (PHYS_ADDR) PCI_MEM_ADRS2,
        PCI_MEM_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
    ,
    {
        (VIRT_ADDR) PCI_MEMIO_ADRS2,
        (PHYS_ADDR) PCI_MEMIO_ADRS2,
        PCI_MEMIO_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
    ,
    {
        (VIRT_ADDR) PCI_IO_ADRS2,
        (PHYS_ADDR) PCI_IO_ADRS2,
        PCI_IO_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
#endif /* INCLUDE_CDS85XX_SECONDARY_PCI */
#endif /* INCLUDE_PCI */
    ,
    {
        (VIRT_ADDR) FLASH1_BASE_ADRS,
        (PHYS_ADDR) FLASH1_BASE_ADRS,
        16 * 1024 *1024,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
        VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
        VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
};

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

/* Clock Ratio Tables */
#define MAX_VALUE_PLAT_RATIO 32
UINT32 platRatioTable[MAX_VALUE_PLAT_RATIO][2] = 
{
    { 0, 0},
    { 0, 0},
    { 2, 0},
    { 3, 0},
    { 4, 0},
    { 5, 0},
    { 6, 0},
    { 7, 0}, 
    { 8, 0},
    { 9, 0},
    { 10, 0},
    { 0, 0},
    { 12, 0},
    { 0, 0},
    { 0, 0},
    { 0, 0},
    { 16, 0},
    { 0, 0} 
};
#define MAX_VALUE_E500_RATIO 8
UINT32 e500RatioTable[MAX_VALUE_PLAT_RATIO][2] = 
{
    { 0, 0},
    { 0, 0},
    { 0, 0},
    { 0, 0},
    { 2, 0},
    { 5, 1},
    { 3, 0},
    { 7, 1} 
};

int   sysBus      = BUS;                /* system bus type (VME_BUS, etc) */
int   sysCpu      = CPU;                /* system CPU type (PPC8260) */
char *sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;   /* catastrophic message area */
int   sysProcNum;           /* processor number of this CPU */
int   sysFlags;             /* boot flags */
char  sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */
BOOL  sysVmeEnable = FALSE;     /* by default no VME */
UINT32  coreFreq;

IMPORT void     mmuE500TlbDynamicInvalidate();
IMPORT void     mmuE500TlbStaticInvalidate();
IMPORT void mmuE500TlbStaticInit (int numDescs, 
                                  TLB_ENTRY_DESC *pTlbDesc, 
                                  BOOL cacheAllow);
IMPORT BOOL     mmuPpcIEnabled;
IMPORT BOOL     mmuPpcDEnabled;

/* forward declarations */

void   sysUsDelay (UINT32);

#ifdef INCLUDE_L1_IPARITY_HDLR_INBSP
    #define _EXC_OFF_L1_PARITY 0x1500
IMPORT void jumpIParity();
IMPORT void sysIvor1Set(UINT32);
UINT32 instrParityCount = 0;
#endif  /* INCLUDE_L1_IPARITY_HDLR_INBSP */


#ifdef INCLUDE_PCI

STATUS sysPciSpecialCycle (int busNo, UINT32 message);
STATUS sysPciConfigRead   (int busNo, int deviceNo, int funcNo,
                           int offset, int width, void * pData);
STATUS sysPciConfigWrite  (int busNo, int deviceNo, int funcNo,
                           int offset, int width, ULONG data);

void   sysPciConfigEnable (int);

#endif /* INCLUDE_PCI */

/* 8260 Reset Configuration Table (From page 9-2 in Rev0 of 8260 book) */
#define END_OF_TABLE 0

UINT32 sysClkFreqGet(void);
UINT32 ppcE500ICACHE_LINE_NUM = (128 * 12);
UINT32 ppcE500DCACHE_LINE_NUM = (128 * 12);

UINT32 ppcE500CACHE_ALIGN_SIZE = 32;

#ifdef INCLUDE_PCI
LOCAL ULONG sysPciConfAddr = PCI_CFG_ADR_REG;   /* PCI Configuration Address */
LOCAL ULONG sysPciConfData = PCI_CFG_DATA_REG;  /* PCI Configuration Data */

    #ifdef INCLUDE_GEI8254X_END
LOCAL int   sysPci1SysNum  = CDS85XX_PCI_1_BUS;
        #ifdef  INCLUDE_CDS85XX_SECONDARY_PCI
LOCAL int   sysPci2SysNum  = CDS85XX_PCI_2_BUS;
        #endif /* INCLUDE_CDS85XX_SECONDARY_PCI */
    #endif /* INCLUDE_GEI8254X_END */

    #include "pci/pciIntLib.c"           /* PCI int support */
    #include "pci/pciConfigLib.c"        /* pci configuration library */

/* use pci auto config */
    #include "pci/pciAutoConfigLib.c"    /* automatic PCI configuration */
    #include "sysBusPci.c"               /* pciAutoConfig BSP support file */
    #include "mot85xxPci.c"

    #ifdef INCLUDE_GEI8254X_END
        #include "sysGei8254xEnd.c"
    #endif  /* INCLUDE_FEI_END */

#endif /* INCLUDE_PCI */

#include "m85xxTimer.c"

#ifdef INCLUDE_NV_RAM
    #include "mem/byteNvRam.c"      /* Generic NVRAM routines */
#endif /* INCLUDE_NV_RAM */

#ifdef INCLUDE_CPM
UINT32 vxImmrGet();
    #include "mem/m82xxDpramLib.c"
#endif

#ifdef INCLUDE_L1_IPARITY_HDLR
    #include "sysL1ICacheParity.c"
#endif

UINT32 inFullVxWorksImage=FALSE;

#define EXT_VEC_IRQ0            56
#define EXT_NUM_IRQ0            EXT_VEC_IRQ0
#define EXT_MAX_IRQS            200

STATUS  sysIntEnablePIC     (int intNum);   /* Enable i8259 or EPIC */
STATUS  sysCascadeIntEnable      (int intNum);
STATUS  sysCascadeIntDisable     (int intNum);
void    flashTest(VUINT16 *address,VUINT16 *buffer,VINT32 length);

UINT32   baudRateGenClk;

#include "sysEpic.c"

#ifdef INCLUDE_DUART
    #include "sysDuart.c"
#endif

#include "sysL2Cache.c"

#ifdef INCLUDE_CPM
void m85xxCpmInt(void);
#endif

#ifdef INCLUDE_CPM
    #include "m8560CpmIntrCtl.c"
#endif

#ifdef INCLUDE_TFFS
    #include "am29lv64xdMtd.c"
#endif /* INCLUDE_TFFS */

#define WB_MAX_IRQS 256

#ifdef  INCLUDE_MOTFCCEND

/* set the following array to a unique Ethernet hardware address */

/* last 5 nibbles are board specific, initialized in sysHwInit */

unsigned char sysFccEnetAddr [2][6] = {{0x08, 0x00, 0x3e, 0x33, 0x02, 0x01},
    {0x08, 0x00, 0x3e, 0x33, 0x02, 0x02}};

STATUS sysFccEnetAddrGet (int unit, UCHAR * address);
#endif  /* INCLUDE_MOTFCCEND */

/* defines */

#define ZERO    0
#define SYS_MODEL_8541    "Freescale CDS MPC8541"
#define SYS_MODEL_8555    "Freescale CDS MPC8555"
#define SYS_MODEL_E500    "Motorola E500 : Unknown system version" 
#define SYS_MODEL_UNKNOWN "Motorola Unknown processor"

/* needed to enable timer base */
#ifdef INCLUDE_PCI
    #define      M8260_DPPC_MASK	0x0C000000 /* bits 4 and 5 */
    #define      M8260_DPPC_VALUE	0x0C000000 /* bits (4,5) should be (1,0) */
#else
    #define      M8260_DPPC_MASK	0x0C000000 /* bits 4 and 5 */
    #define      M8260_DPPC_VALUE	0x08000000 /* bits (4,5) should be (1,0) */
#endif /*INCLUDE_PCI */

#define DELTA(a,b)                 (abs((int)a - (int)b))
#define HID0_MCP 0x80000000
#define HID1_ABE 0x00001000
#define HID1_ASTME 0x00002000

#ifdef  INCLUDE_MOTFCCEND
    #include "sysMotFcc2End.c"
#endif /* INCLUDE_MOTFCCEND */

#ifdef INCLUDE_MOT_TSEC_END
    #include "sysMotTsecEnd.c"
#endif /* INCLUDE_MOT_TSEC_END */

#ifdef INCLUDE_BRANCH_PREDICTION