sysgei8254xend.c

Freescale MPC85xx BSP (8555/8541)。绝对可用的。

/* sysGei82543End.c - Intel 82540/82543/82544/82545/82546 END support routine */

/* Copyright 1989-2004 Wind River Systems, Inc.  */

/*
modification history
--------------------
01b,22mar05,dtr  Fix typos.
01a,04nov04,jln  ported from 01n/sysGei82543End.c/pc386
*/

/*
This module is the WRS-supplied configuration module for Intel PRO1000
F/T/XF/XT/MT/MF adapters. It has routines for initializing device resources
and provides BSP-specific gei82543End (gei) END driver routines for
Intel 82540/3/4/5/6 Ethernet PCI bus controllers.

The number of supported devices that can be configured for a particular
system is finite and is specified by the GEI_MAX_DEV configuration
constant.  This value, and the internal data structures using it, can be
modified in this file for specific implementations.

SEE ALSO: ifLib,
.I "RS82543GC GIGABIT ETHERNET CONTROLLER NETWORKING SILICON DEVELOPER'S MANUAL"
*/


#if defined(INCLUDE_GEI8254X_END)

/* namespace collisions */

#undef INTEL_PCI_VENDOR_ID  /* redefined in gei82543End.h (temporary fix) */

/* includes */

#include "end.h"
#include "drv/end/gei82543End.h"

/* defines */

/* specify the maximum number of physical devices to configure */

#define GEI_MAX_DEV      (4)

/* Default RX descriptor  */

#ifndef GEI_RXDES_NUM
#define GEI_RXDES_NUM              (GEI_DEFAULT_RXDES_NUM)
#endif

/* Default TX descriptor  */

#ifndef GEI_TXDES_NUM
#define GEI_TXDES_NUM              (GEI_DEFAULT_TXDES_NUM)
#endif

/* Default User's flags  */

/* ORed the flag of GEI_END_JUMBO_FRAME_SUPPORT if jumbo frame needed */

#ifndef GEI_USR_FLAG
#define GEI_USR_FLAG        (GEI_END_SET_TIMER | \
                             GEI_END_SET_RX_PRIORITY | \
                             GEI_END_FREE_RESOURCE_DELAY \
                            )
#endif /* GEI_USR_FLAG */

/* 
 * If jumbo frame supported, the default 9000 bytes of MTU will be used. 
 * Otherwise 1500 bytes MTU for normal frames. User can set up different 
 * MTU here for jumbo frames. 
 */

#ifndef GEI_JUMBO_MTU_VALUE
#define GEI_JUMBO_MTU_VALUE         (0)  /* Will use default value (9000) */
#endif /* GEI_JUMBO_MTU_VALUE */

/*
 * define the offset value for different arches.
 * For arch like ARM which requires 4-byte alignment for Integer, 
 * use offset of 2
 */

#define GEI_X86_OFFSET_VALUE        (0x0)
#define GEI_ARM_OFFSET_VALUE        (0x2)

#ifndef GEI_OFFSET_VALUE
#define GEI_OFFSET_VALUE            GEI_X86_OFFSET_VALUE 
#endif /* GEI_OFFSET_VALUE */

/* Assuming 1:1 mapping */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#define GEI_SYS_WRITE_REG(unit, reg, value)     \
   ((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow + reg))) = \
    (LONGSWAP((UINT32)(value))))

#define GEI_SYS_READ_REG(unit, reg)             \
   LONGSWAP((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow + reg))))

#else

#define GEI_SYS_WRITE_REG(unit, reg, value)     \
   ((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow + reg))) = \
    (UINT32)(value))

#define GEI_SYS_READ_REG(unit, reg)             \
   (*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow + reg)))

#endif /* _BYTE_ORDER */

/* PCI device ID for Intel 82543/82544 Ethernet */

#define PRO1000_543_PCI_DEVICE_ID_T     (0x1001) /* Copper */
#define PRO1000_543_PCI_DEVICE_ID_FT    (0x1004) /* Fiber / Copper */
#define PRO1000_544_PCI_DEVICE_ID_XT    (0x1008) /* Copper */
#define PRO1000_544_PCI_DEVICE_ID_XF    (0x1009) /* Fiber */
#define PRO1000_544_PCI_DEVICE_ID_GC    (0x100c) /* Copper */
#define PRO1000_540_PCI_DEVICE_ID_XT    (0x100e) /* Copper only */
#define PRO1000_545_PCI_DEVICE_ID_XT    (0x100f) /* Copper */
#define PRO1000_546_PCI_DEVICE_ID_XT    (0x1010) /* Copper - 82546 EB */
#define PRO1000_545_PCI_DEVICE_ID_MF    (0x1011) /* Fiber */
#define PRO1000_546_PCI_DEVICE_ID_MF    (0x1012) /* Fiber */
#define PRO1000_546_PCI_DEVICE_ID_XT2   (0x1079) /* Copper - 82546 GB */

/* device resources */

#define GEI_MEMSIZE_CSR            (0x20000)     /* 128Kb CSR memory size */
#define GEI_MEMSIZE_FLASH          (0x80000)     /* 512Kb Flash memory size */
#define GEI_EEPROM_SZ_64           (64)          /* 64 WORD */   
#define GEI_EEPROM_SZ_256          (256)         /* 256 WORD */   

#define GEI0_SHMEM_BASE             NONE
#define GEI0_SHMEM_SIZE             (0)
#define GEI0_RXDES_NUM              GEI_RXDES_NUM
#define GEI0_TXDES_NUM              GEI_TXDES_NUM
#define GEI0_USR_FLAG               GEI_USR_FLAG

#define GEI1_SHMEM_BASE             NONE
#define GEI1_SHMEM_SIZE             (0)
#define GEI1_RXDES_NUM              GEI_RXDES_NUM
#define GEI1_TXDES_NUM              GEI_TXDES_NUM
#define GEI1_USR_FLAG               GEI_USR_FLAG

#define GEI2_SHMEM_BASE             NONE
#define GEI2_SHMEM_SIZE             (0)
#define GEI2_RXDES_NUM              GEI_RXDES_NUM
#define GEI2_TXDES_NUM              GEI_TXDES_NUM
#define GEI2_USR_FLAG               GEI_USR_FLAG

#define GEI3_SHMEM_BASE             NONE
#define GEI3_SHMEM_SIZE             (0)
#define GEI3_RXDES_NUM              GEI_RXDES_NUM
#define GEI3_TXDES_NUM              GEI_TXDES_NUM
#define GEI3_USR_FLAG               GEI_USR_FLAG

/* INTEL 82544 INTERNAL PHY */

#define INTEL_82544PHY_OUI_ID                   (0x5043)
#define INTEL_82544PHY_MODEL                    (0x3)

#define INTEL_82544PHY_PHY_SPEC_CTRL_REG        (0x10)
#define INTEL_82544PHY_PHY_SPEC_STAT_REG        (0x11)
#define INTEL_82544PHY_INT_ENABLE_REG           (0x12)
#define INTEL_82544PHY_INT_STATUS_REG           (0x13)
#define INTEL_82544PHY_EXT_PHY_SPEC_CTRL_REG    (0x14)
#define INTEL_82544PHY_RX_ERROR_COUNTER         (0x15)
#define INTEL_82544PHY_PHY_GLOBAL_STAT          (0x17)
#define INTEL_82544PHY_LED_CTRL_REG             (0x18)

#define INTEL_82544PHY_PSCR_ASSERT_CRS_ON_TX    (0x0800)
#define INTEL_82544PHY_EPSCR_TX_CLK_25          (0x0070)

/* Alaska PHY's information */

#define MARVELL_OUI_ID                  (0x5043)
#define MARVELL_ALASKA_88E1000          (0x5)
#define MARVELL_ALASKA_88E1000S         (0x4)
#define ALASKA_PHY_SPEC_CTRL_REG        (0x10)
#define ALASKA_PHY_SPEC_STAT_REG        (0x11)
#define ALASKA_INT_ENABLE_REG           (0x12)
#define ALASKA_INT_STATUS_REG           (0x13)
#define ALASKA_EXT_PHY_SPEC_CTRL_REG    (0x14)
#define ALASKA_RX_ERROR_COUNTER         (0x15)
#define ALASKA_LED_CTRL_REG             (0x18)

#define ALASKA_PSCR_ASSERT_CRS_ON_TX    (0x0800)
#define ALASKA_EPSCR_TX_CLK_25          (0x0070)

#define ALASKA_PSCR_AUTO_X_1000T        (0x0040)
#define ALASKA_PSCR_AUTO_X_MODE         (0x0060)

#define ALASKA_PSSR_DPLX                (0x2000)
#define ALASKA_PSSR_SPEED               (0xC000)
#define ALASKA_PSSR_10MBS               (0x0000)
#define ALASKA_PSSR_100MBS              (0x4000)
#define ALASKA_PSSR_1000MBS             (0x8000)

#ifndef BOARD_TYPE_UNKNOWN
#define BOARD_TYPE_UNKNOWN (-1)
#endif /* BOARD_TYPE_UNKNOWN */

/* typedefs */

typedef struct geiResource        /* GEI_RESOURCE */
    {
    BOOL   adr64;                 /* Indicator for 64-bit support */
    UINT32 memBaseLow;            /* Base Address LOW */
    UINT32 memBaseHigh;           /* Base Address HIGH */
    UINT32 flashBase;             /* Base Address for FLASH */

    UINT16 eepromSize;            /* size in unit of word (16 bit) - 64/256 */ 
    UINT16 eeprom_icw1;           /* EEPROM initialization control word 1 */
    UINT16 eeprom_icw2;           /* EEPROM initialization control word 2 */
    UCHAR  enetAddr[6];           /* MAC address for this adaptor */

    UINT32 shMemBase;             /* Share memory address if any */
    UINT32 shMemSize;             /* Share memory size if any */

    UINT32 rxDesNum;              /* RX descriptor for this unit */
    UINT32 txDesNum;              /* TX descriptor for this unit */

    BOOL   useShortCable;         /* TRUE if short cable used for 82544 */
                                     /* by default is FALSE */
    UINT32 usrFlags;              /* user flags for this unit */
    STATUS iniStatus;             /* initialization perform status */

    } GEI_RESOURCE;
 
/* typedefs */

typedef struct pciBoardResource      /* PCI_BOARD_RESOURCE */
    {
    int           pciSysNum;         /* PCI system number */
    UINT32        pciBus;            /* PCI Bus number */
    UINT32        pciDevice;         /* PCI Device number */
    UINT32        pciFunc;           /* PCI Function number */

    UINT32        vendorID;          /* PCI Vendor ID */
    UINT32        deviceID;          /* PCI Device ID */
    UINT8         revisionID;        /* PCI Revision ID */
    UINT32        boardType;         /* BSP-specific board type ID */

    UINT8         irq;               /* Interrupt Request Level */
    UINT32        irqvec;            /* Interrupt Request vector */

    UINT32        bar [6];           /* PCI Base Address Registers */

    void * const  pExtended;         /* pointer to extended device info */

    } PCI_BOARD_RESOURCE;

/* locals */

LOCAL int geiUnits = 0;     /* number of GEIs we found */

/* This table defined board extended resources */

LOCAL GEI_RESOURCE geiResources [GEI_MAX_DEV] =
    {
    {FALSE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, GEI_EEPROM_SZ_64, 0, 0, {(UCHAR)NONE},
     (UINT32)GEI0_SHMEM_BASE, GEI0_SHMEM_SIZE, GEI0_RXDES_NUM, GEI0_TXDES_NUM, FALSE, 
     GEI0_USR_FLAG, ERROR
    },

    {FALSE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, GEI_EEPROM_SZ_64, 0, 0, {(UCHAR)NONE},
     (UINT32)GEI1_SHMEM_BASE, GEI1_SHMEM_SIZE, GEI1_RXDES_NUM, GEI1_TXDES_NUM, FALSE, 
     GEI1_USR_FLAG, ERROR
    },

    {FALSE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, GEI_EEPROM_SZ_64, 0, 0, {(UCHAR)NONE},
     (UINT32)GEI2_SHMEM_BASE, GEI2_SHMEM_SIZE, GEI2_RXDES_NUM, GEI2_TXDES_NUM, FALSE, 
     GEI2_USR_FLAG, ERROR
    },

    {FALSE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, GEI_EEPROM_SZ_64, 0, 0, {(UCHAR)NONE},
     (UINT32)GEI3_SHMEM_BASE, GEI3_SHMEM_SIZE, GEI3_RXDES_NUM, GEI3_TXDES_NUM, FALSE, 
     GEI3_USR_FLAG, ERROR
    }
    };

/* This table defines board PCI resources */

LOCAL PCI_BOARD_RESOURCE geiPciResources [GEI_MAX_DEV] =
    {
    {NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE,
    {(UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE},
     (void * const)(&geiResources[0])
    },

    {NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE,
    {(UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE},
     (void * const)(&geiResources[1])
    },

    {NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE,
    {(UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE},
     (void * const)(&geiResources[2])
    },

    {NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE, (UINT8)NONE, (UINT32)NONE,
    {(UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE, (UINT32)NONE},
     (void * const)(&geiResources[3])
    }
    };

/* forward declarations */

LOCAL int       sys543IntEnable  (int unit);
LOCAL int       sys543IntDisable (int unit);
LOCAL int       sys543IntAck     (int unit);
LOCAL STATUS    sys543eepromCheckSum (int unit);
LOCAL UINT16    sys543eepromReadWord (int unit,UINT32);
LOCAL STATUS    sys543EtherAdrGet (int unit);
LOCAL void      sys544PhyPreInit (PHY_INFO *);
LOCAL void      sys543PhySpecRegsInit(PHY_INFO *, UINT8);
LOCAL BOOL      sysGei82546InitTimerSetup (ADAPTOR_INFO * ); 
LOCAL BOOL      sysGei82546DynaTimerSetup (ADAPTOR_INFO * ); 
LOCAL UINT32    sysGeiDevToType (UINT32, UINT32, UINT8);
LOCAL void      sysGei543UsDelay (void);

STATUS sys543PciInit (UINT32,UINT32,UINT32,UINT32,UINT32,UINT8,UINT32,int);  

/*****************************************************************************
* sys8254xDeviceCheck - check whether a device is 8254x
*
* This function verifies a device is Intel 8254x
*
* RETURN: OK
*/

STATUS sys8254xDeviceCheck
    (
    UINT32              pciBus,        /* store a PCI bus number */
    UINT32              pciDevice,     /* store a PCI device number */
    UINT32              pciFunc,       /* store a PCI function number */
    void *              pPciSysNum     /* reserved argument */
    )
    {
    UINT32        boardType;   /* store a BSP-specific board type constant */

    UINT32        vendorId;    /* store a PCI vendor ID */
    UINT32        deviceId;    /* store a PCI device ID */
    UINT8         revisionId;  /* store a PCI revision ID */

    pciConfigInLong (pciBus, pciDevice, pciFunc,
                      PCI_CFG_VENDOR_ID, &vendorId);

    pciConfigInByte (pciBus, pciDevice, pciFunc,
                         PCI_CFG_REVISION, &revisionId);

    deviceId = ((vendorId >> 16) & 0x0000ffff);
    vendorId = (vendorId & 0x0000ffff);

    if ((boardType = sysGeiDevToType (vendorId, deviceId, revisionId))
                  != (UINT32)(BOARD_TYPE_UNKNOWN))
        {

        int pciSysNum = *(int *)pPciSysNum;

        sys543PciInit (pciBus, pciDevice, pciFunc, vendorId, 
                        deviceId, revisionId, boardType, pciSysNum);
        } 

    return OK;
    }

/*****************************************************************************
*
* sys543PciInit - initialize a GEI 8254x PCI ethernet device
*
* This routine performs basic PCI initialization for 8254x ethernet
* devices supported by the gei82543End END driver.  Parameters to this
* routine specify a PCI function, including PCI ID registers, to
* initialize.  If supported,  the device memory and I/O addresses are
* mapped into the local CPU address space and an internal board-specific
* PCI resources table is updated with information on the board type,
* memory address, and IO address.
*
* RETURNS:
* OK, or ERROR if the specified device is not supported, or if
* the device could not be mapped into the local CPU memory space.
*/
STATUS sys543PciInit
    (
    UINT32         pciBus,      /* store a PCI bus number */
    UINT32         pciDevice,   /* store a PCI device number */