sysmotfcc2end.c

Freescale MPC85xx BSP (8555/8541)。绝对可用的。

    int      * pDuplex
    )
    {
    UINT16 miiStat;
    int    retVal;

    MII_READ(pPhyInfo->phyAddr,17,&miiStat,retVal);

    if (retVal == OK)
    {
    *pDuplex = (miiStat & 0x200) ? 1 : 0;
        }
    return retVal;
    }

/***********************************************************************
*
* sysMiiInt - MII interrupt service routine
*
* This routine check if the link up or down and update a flag
*
* RETURNS: None.
*/

LOCAL void sysMiiInt
    (
    PHY_INFO * pPhyInfo
    )
    {
    UINT16 miiIntStatusReg;
    int    tmp;

    /* Clear MII interrupt by reading Int status reg */
    MII_READ(pPhyInfo->phyAddr,19,&miiIntStatusReg,tmp);
    ++miiNumLinkChgInts;

    }

/***********************************************************************
*
* sysMiiPhyInit - initialize and configure the PHY devices
*
* This routine scans, initializes and configures the PHY device.
*
* RETURNS: OK, or ERROR.
*/

LOCAL STATUS sysMiiPhyInit
    (
    PHY_INFO * pPhyInfo
    )
    {
    int    retVal,retValNull;
    VUINT16 miiSpecial;

    retVal = miiPhyInit (pPhyInfo);

    /* Set reg 16 of MII to proper default */
    miiSpecial = 0x0400; /* Base-TX */
    MII_WRITE(pPhyInfo->phyAddr,16,miiSpecial,retValNull);

    return retVal;
    }

/***********************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to enable the Ethernet device and to connect the MII interface to the FCC.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/

STATUS sysFccEnetEnable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    volatile UINT32 tmp;
    int             intLevel;

    intLevel = intLock ();
    /* set Port B and C to use MII signals */

    *M8260_IOP_PBPAR(immrVal) &= ~(PB15 | PB14);    /* clear PAR bits for xcvr RST and PWRDWN pins */
    *M8260_IOP_PBDIR(immrVal) |=  (PB15 | PB14);    /* make them outputs */

    tmp = *M8260_IOP_PBDAT(immrVal);            /* get current port B data */
    tmp &= ~(PB14);                 /* drive the active high PWRWN pin low */
    tmp &= ~(PB15);                 /* drive the active low RST low too, for now */
    *M8260_IOP_PBDAT(immrVal) = tmp;

    if (fccNum==2)
      {
	*M8260_IOP_PCPAR(immrVal) |=  (PC19 | PC18);
	*M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
	*M8260_IOP_PCSO(immrVal)  &= ~(PC19 | PC18);
	*M8260_IOP_PCDIR(immrVal) &= ~(PC19 | PC18);

	*M8260_IOP_PBPAR(immrVal) |=  (PB31 | PB30 | PB29 | PB28 | PB27 | 
				       PB26 | PB25 | PB24 | PB23 | PB22 | 
				       PB21 | PB20 | PB19 | PB18);
	*M8260_IOP_PBDIR(immrVal) |=  (PB31 | PB29 | PB25 | PB24 | PB23 | 
				       PB22);
	*M8260_IOP_PBDIR(immrVal) &= ~(PB30 | PB28 | PB27 | PB26 | PB21 | 
				       PB20 | PB19 | PB18);
	*M8260_IOP_PBSO(immrVal)  &= ~(PB31 | PB30 | PB28 | PB27 | PB26 | 
				       PB25 | PB24 | PB23 | PB22 | PB21 | 
				       PB20 | PB19 | PB18);
	*M8260_IOP_PBSO(immrVal)  |=  (PB29);

	/* connect FCC2 clocks */

	*M8260_CMXFCR (immrVal)  |= (M8260_CMXFCR_R2CS_CLK13 | 
				     M8260_CMXFCR_T2CS_CLK14);
	*M8260_CMXFCR (immrVal)  &= ~(M8260_CMXFCR_FC2_MUX);
    }

    if (fccNum==3)
      {
	*M8260_IOP_PDSO(immrVal) |= PD4;	
	*M8260_IOP_PCSO(immrVal) &= ~(PC17 | PC16);	
	*M8260_IOP_PBDIR(immrVal) |= (PB15 | PB14 | PB7 | PB6 | PB5 | PB4);
	*M8260_IOP_PCDIR(immrVal) |= (PC27);	
	*M8260_IOP_PDDIR(immrVal) |= (PD4);	
	*M8260_IOP_PCPAR(immrVal) |= (PC16 | PC17);	
	*M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);	
	*M8260_IOP_PCPAR(immrVal) |= (PC3 | PC2 | PC27);	
	*M8260_IOP_PBPAR(immrVal) |= (PB17 | PB16 | PB15 | PB14 | PB13 | 
				      PB12 | PB11 | PB10 | PB9  | PB8  | 
				      PB7  | PB6  | PB5  | PB4);	
	*M8260_IOP_PDPAR(immrVal) |= (PD4);	
    
	/* connect FCC3 clocks */

	*M8260_CMXFCR (immrVal)  |= (M8260_CMXFCR_R3CS_CLK15 | 
				 M8260_CMXFCR_T3CS_CLK16);

	/* NMSI mode */

	*M8260_CMXFCR (immrVal)  &= ~(M8260_CMXFCR_FC3_MUX);         
      }

    tmp = *M8260_IOP_PBDAT(immrVal); /* get current port B data */
    tmp |=  (PB15);                  /* drive the active low RST high */
    *M8260_IOP_PBDAT(immrVal) = tmp;

    intUnlock (intLevel);

    taskDelay (sysClkRateGet() >> 2);


    return(OK);
    }

/***********************************************************************
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller.  This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/

STATUS sysFccEnetDisable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    volatile UINT32 tmp;
    int             intLevel;

    intLevel = intLock ();

    /*
     * configure all Port B and C pins previously used as general
     * purpose input pins
     */

    *M8260_IOP_PBPAR(immrVal) &= ~(PB15 | PB14);    /* clear PAR bits for xcvr RST and PWRDWN pins */
    *M8260_IOP_PBDIR(immrVal) |=  (PB15 | PB14);    /* make them outputs */

    tmp = *M8260_IOP_PBDAT(immrVal);        /* get current port B data */
    tmp |=  (PB14);         /* drive the active high PWRWN pin high */
    tmp &= ~(PB15);         /* drive the active low RST low too */
    *M8260_IOP_PBDAT(immrVal) = tmp;

    *M8260_IOP_PCPAR(immrVal) &= ~(PC19 | PC18);

    *M8260_IOP_PCDIR(immrVal) &= ~(PC10);

    *M8260_IOP_PBPAR(immrVal) &= ~(PB31 | PB30 | PB29 | PB28 | PB27 | PB26 | PB25 |
                                   PB24 | PB23 | PB22 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBDIR(immrVal) &= ~(PB31 | PB29 | PB25 | PB24 | PB23 | PB22);

    /* Disable the interrupt */
    m85xxCpmIntDisable (INUM_FCC2);

    intUnlock (intLevel);

    return(OK);
    }


/***********************************************************************
*
* sysFccEnetCommand - issue a command to the Ethernet interface controller
*
* RETURNS: OK, or ERROR if the Ethernet controller could not be restarted.
*/

STATUS sysFccEnetCommand
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    UINT16  command
    )
    {
    return (OK);
    }

#ifndef NSDELAY
#define MOTOROLA_FCC_LOOP_NS 2

#define NSDELAY(nsec)                                                   \
    {                                                                   \
    volatile int nx = 0;                                                \
    volatile int loop = (int)(nsec*MOTOROLA_FCC_LOOP_NS);               \
                                                                        \
    for (nx = 0; nx < loop; nx++);                                      \
    }
#endif /* NSDELAY */

/***********************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/
STATUS sysFccMiiBitWr
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT32        bitVal          /* the bit being written */
    )
    {
    miiBitWrCount++;
    /*
     * we create the timing reference for transfer of info on the MDIO line
     * MDIO is mapped on PC9, MDC on PC10. We need to keep the same data
     * on MDIO for at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCDIR(immrVal) |= (PC10 | PC9);
    *M8260_IOP_PCDAT(immrVal) |= (PC10);

    switch (bitVal)
    {
    case 0:
        *M8260_IOP_PCDAT(immrVal) &= ~(PC9);
        break;
    case 1:
        *M8260_IOP_PCDAT(immrVal) |= (PC9);
        break;
    case ((INT32) NONE):
        /* put it in high-impedance state */
        *M8260_IOP_PCDIR(immrVal) &= ~(PC9);
        break;
    default:
        return (ERROR);
    }

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC10);

    NSDELAY (200);

    return (OK);
    }

/***********************************************************************
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitRd
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT8 *      bitVal          /* the bit being read */
    )
    {
    miiBitRdCount++;
    /*
     * we create the timing reference for transfer of info on the MDIO line
     * MDIO is mapped on PC9, MDC on PC10. We can read data on MDIO after
     * at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC9);

    *M8260_IOP_PCDIR(immrVal) |= (PC10);
    *M8260_IOP_PCDAT(immrVal) |= (PC10);

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC10);

    NSDELAY (200);

    /* we can now read the MDIO data on PC9 */

    *bitVal = (*M8260_IOP_PCDAT(immrVal) & (PC9)) >> 22;

    return (OK);
    }

#endif /* INCLUDE_MOTFCCEND */

UINT32 m8260InumToIvec(UINT32 val)
{
return val;
}