rominit.s

Freescale MPC85xx BSP (8555/8541)。绝对可用的。

/* romInit.s - ROM bootcode for ads85xx BSP */
	
/* Copyright 1984-2004 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01m,04sep04,jln  supported ads85xx
01l,03aug04,dtr  Add workaround for LBC errata #11.
01k,29jul04,dtr  Reset TLB to not guarded after DDR/LBC init.
	         Implement workaround for errata DDR#11.  
01j,22jul04,dtr  Improve boot time by enabling ICACHE.
01i,03feb04,dtr  Mod for DDR issue.
01h,28oct03,dtr  Change OR value for ADS_PROTOTYPE.
01g,08oct03,dtr  Errata related to local bus DLL.
01f,12sep03,dtr  Removing CAM entry for PCI.
01e,02sep03,dtr  Remove zero of PID2 due to errata.
01d,05aug03,dtr  Adding SDRAM support.
01c,29jul03,dtr  Remove some magic numbers CCSBAR.
01b,22jul03,mil  Saved boot type and allow cold boot.
01a,03oct02,dtr  Created.
*/
	.data
#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "arch/ppc/mmuE500Lib.h"		

FUNC_EXPORT(romInit)
FUNC_EXPORT(_romInit)
	
FUNC_IMPORT(romStart)

#define WRITEADR(reg1,reg2,addr32,val) \
	lis	reg1, HI(addr32); \
	ori	reg1, reg1, LO(addr32); \
	lis	reg2, HI(val); \
	ori	reg2, reg2, LO(val); \
	stw	reg2, 0(reg1)

#define WRITEOFFSET(regbase,reg2,offset,val) \
        lis	reg2, HI(val); \
        ori	reg2, reg2, LO(val); \
	stw	reg2, offset(regbase);
	
	_WRS_TEXT_SEG_START
	
	.fill 0x100,1,0
	
FUNC_BEGIN(romInit)	
FUNC_BEGIN(_romInit)
	bl     resetEntry

romWarm:
	bl     warm

        .ascii   "Copyright 1984-2002 Wind River Systems, Inc."
        .balign 4

cold:
	li    r2, BOOT_COLD
	b     start
	/* defines for memory initialization */
warm:
	mr     r2,r3

start:	
        /* turn off exceptions */
        mfmsr   r3                      /* r3 = msr              */
        INT_MASK (r3, r4)               /* mask EE and CE bit    */
        rlwinm  r4, r4, 0, 20, 18       /* turn off _PPC_MSR_ME  */
        mtmsr   r4                      /* msr = r4              */
        isync

        xor     r0, r0, r0
        addi    r1, r0, -1

        mtspr   DEC, r0
        mtspr   TBL, r0
        mtspr   TBU, r0
        mtspr   TSR, r1
        mtspr   TCR, r0
        mtspr   ESR, r0                 /* clear Exception Syndrome Reg */
        mtspr   XER, r0                 /*  clear Fixed-Point Exception Reg */

	xor   r6, r6, r6
	msync
	isync
	mtspr L1CSR0, r6		/* Disable the Data cache */
        li   r6, 0x0002              
	msync
	isync
	mtspr L1CSR0, r6		/* Invalidate the Data cache */
        li    r6, 0x0000              
        msync
	isync
	mtspr L1CSR1, r6	 /* Disable the Instrunction cache */
        li   r6, 0x0002              
        msync
	isync
	mtspr L1CSR1, r6	/* Invalidate the Instruction cache */
        isync
        li   r6, 0x0000              
	msync
	isync
	mtspr L1CSR1, r6        /* temp disabled Enable the Instruction cache*/
#if defined(INCLUDE_CACHE_SUPPORT) && defined(USER_I_CACHE_ENABLE)
        isync
        li	r7, 0x0001
	msync
	isync
	mtspr	L1CSR1, r7		/* enable the instruction cache */
#endif  /* INCLUDE_CACHE_SUPPORT && USER_I_CACHE_ENABLE */
	msync
	isync
#ifdef INCLUDE_PCI
        /* Set the pciAutoconfig check to FALSE */
	xor     r5,r5,r5                /* Zero r5 */
	lis     r6,HIADJ(PCI_AUTO_CONFIG_ADRS)                   
	addi	r6,r6,LO(PCI_AUTO_CONFIG_ADRS)
	stw     r5,0(r6)
#endif /* INCLUDE_PCI */
	
	xor     r6,r6,r6
	xor     r7,r7,r7
	mullw   r7,r7,r6
        lis     sp, HI(STACK_ADRS)
        ori     sp, sp, LO(STACK_ADRS)
        addi    sp, sp, -FRAMEBASESZ
        lis     r6, HI(romInit)
        ori     r6, r6, LO(romInit)
        lis     r7, HI(romStart)
        ori     r7, r7, LO(romStart)
        lis     r8, HI(ROM_TEXT_ADRS)
        ori     r8, r8, LO(ROM_TEXT_ADRS)
	sub	r6, r7, r6		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */
        mtspr   LR, r6

        mr      r3, r2
        blr 
FUNC_END(_romInit)
FUNC_END(romInit)


/***************************************************************************
*
* resetEntry - rom entry point
*
*
*/

#if   defined(_GNU_TOOL)
	.section .boot, "ax", @progbits
#elif defined(_DIAB_TOOL)
        .section .boot, 4, "rx"
#else
#error "Please add a correctly spelled .section directive for your toolchain."
#endif

FUNC_BEGIN(resetEntry)
FUNC_LABEL(_resetEntry)

		
        /* Clear SRR0, CSRR0, MCSRR0, SRR1, CSRR1 , MCSRR1, IVPR */

	xor   r0,r0,r0
        mtspr SRR0, r0
        mtspr SRR1, r0
        mtspr CSRR0, r0
        mtspr CSRR1, r0
        mtspr MCSRR0, r0
        mtspr MCSRR1, r0
        mtspr IVPR, r0

        /* Set up vector offsets */
        addi  r3, r0, 0x100
        mtspr IVOR0, r3
        addi  r3, r0, 0x200
        mtspr IVOR1, r3
        addi  r3, r0, 0x300
        mtspr IVOR2, r3
        addi  r3, r0, 0x400
        mtspr IVOR3, r3
        addi  r3, r0, 0x500
        mtspr IVOR4, r3
        addi  r3, r0, 0x600
        mtspr IVOR5, r3
        addi  r3, r0, 0x700
        mtspr IVOR6, r3
        /* skipping IVOR7 0x800: no FPU on e500 */
        addi  r3, r0, 0x900
        mtspr IVOR8, r3
        /* skipping IVOR9 0xa00: no aux processor on e500 */
        addi  r3, r0, 0xb00
        mtspr IVOR10, r3
        addi  r3, r0, 0xc00
        mtspr IVOR11, r3
        addi  r3, r0, 0xd00
        mtspr IVOR12, r3
        addi  r3, r0, 0xe00
        mtspr IVOR13, r3
        addi  r3, r0, 0xf00
        mtspr IVOR14, r3
        addi  r3, r0, 0x1000
        mtspr IVOR15, r3
        addi  r3, r0, 0x1100       /* SPU is e500 specific */
        mtspr IVOR32, r3
        addi  r3, r0, 0x1200       /* FP data is e500 specific */
        mtspr IVOR33, r3
        addi  r3, r0, 0x1300       /* FP round is e500 specific */
        mtspr IVOR34, r3
        addi  r3, r0, 0x1400       /* perf mon is e500 specific */
        mtspr IVOR35, r3

        /* Initialize PID reg to match TID field of TLB entry (unless using TID=0) */

	xor   r0,r0,r0
	mtspr PID0 , r0
	mtspr PID1 , r0
	/*mtspr PID2 , r0 comment out for now due to suspected errata*/

        /*
         * Write TLB entry for initial program memory page
         *
         * - Specify EPN, RPN, and TSIZE as appropriate for system
         * - Set valid bit
         * - Specify TID=0
         * - Specify TS=0 or else MSR[IS,DS] must be set to correspond to TS=1
         * - Specify storage attributes (W, I, M, G, E, U0 - U3) as appropriate
         * - Enable supervisor mode fetch, read, and write access (SX, SR, SW)
         */

        /*
         * TLB1 #0.  ROM/CCSBAR - non-cached 0xf0000000 -> 0xf00000000.  
	 * 256MB
         * Attributes: SX/SW/SR **PROTECTED**
         */

        addis  r4,0,0x1000           /* TLBSEL = TLB1(CAM) , ESEL = 0 */ 
        ori    r4,r4,0x0000
        mtspr  MAS0, r4
        addis  r5,0,0xc000           /* V = 1, IPROT = 1, TID = 0*/
        ori    r5,r5,_MMU_TLB_SZ_256M  /* TS = 0, TSIZE = 256 MByte page size*/
        mtspr  MAS1, r5
        addis  r6,0,0xf000           /* EPN = 0xf0000000*/
        ori    r6,r6,0x000a          /* WIMGE = 01010 */
        mtspr  MAS2, r6
        addis  r7,0,0xf000           /* RPN = 0xf0000000*/
        ori    r7,r7,0x0015          /* Supervisor XWR*/
        mtspr  MAS3, r7
        tlbwe         
        tlbsync                     

        /*
         * TLB1 #1.  Main SDRAM - Not Cached
	 *           LOCAL_MEM_LOCAL_ADRS -> LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE
         * Attributes: UX/UW/UR/SX/SW/SR
         */

        addis  r4,0,0x1001           /* TLBSEL = TLB1(CAM) , ESEL = 1*/
        ori    r4,r4,0x0000
        mtspr  MAS0, r4
        addis  r5,0,0xc000           /* V = 1, IPROT = 1, TID = 0*/
        ori    r5,r5,_MMU_TLB_SZ_256M  /* TS = 0, TSIZE = 256 MByte page size*/
        mtspr  MAS1, r5
        addis  r6,0,HI(LOCAL_MEM_LOCAL_ADRS) /* EPN = LOCAL_MEM_LOCAL_ADRS */
        ori    r6,r6,0x000a          /* WIMGE = 01010*/
        mtspr  MAS2, r6
        addis  r7,0,HI(LOCAL_MEM_LOCAL_ADRS)  /* RPN = LOCAL_MEM_LOCAL_ADRS */
        ori    r7,r7,0x003f          /* User/Supervisor XWR*/
        mtspr  MAS3, r7
        tlbwe                       
        tlbsync                      
	
        /*
         * TLB1 #2.  Additional SDRAM - not cached 
	 *           LOCAL_MEM_LOCAL_ADRS2 -> LOCAL_MEM_LOCAL_ADRS2 + LOCAL_MEM_SIZE
         * Attributes: UX/UW/UR/SX/SW/SR
         */

        addis  r4,0,0x1002          /* TLBSEL = TLB1(CAM) , ESEL = 2*/
        ori    r4,r4,0x0000
        mtspr  MAS0, r4
        addis  r5,0,0x8000           /* V = 1, IPROT = 0, TID = 0*/
        ori    r5,r5,_MMU_TLB_SZ_64M /* TS = 0, TSIZE = 64 MByte page size*/
        mtspr  MAS1, r5
        addis  r6,0,HI(LOCAL_MEM_LOCAL_ADRS2) /* EPN = LOCAL_MEM_LOCAL_ADRS2 */
        ori    r6,r6,0x000a          /* WIMGE = 01010 */
        mtspr  MAS2, r6

        addis  r7,0,HI(LOCAL_MEM_LOCAL_ADRS2) /* RPN = LOCAL_MEM_LOCAL_ADRS2 */
        ori    r7,r7,0x0015          /* Supervisor XWR*/
        mtspr  MAS3, r7
        tlbwe                       
        tlbsync                      
	
	/* Setup the memory mapped register address */
	WRITEADR(r6,r7,0xFF700000,(CCSBAR >> 12)) 
	sync
	isync
	
	/* Initialise the Local Bus Controller */

	WRITEADR(r6,r7,M85XX_LCRR(CCSBAR),0x00030008) 
	
	/* Set override for DDR */ 
	WRITEADR(r6,r7,M85XX_DDRDLLCR(CCSBAR),0x81000000) 

/* Store DLL setting and override  so as to avoid glitches in local bus 
   due to errata. Start with delay to allow DLL to stabilize ~ 200us 
   for 1GHz */
	lis     r6, 0x3
	mtctr   r6
delayLoop:
	bdnz    delayLoop

	/* Read LBC DLL and get tap reading */	
        lis     r6, HIADJ(M85XX_LBCDLLSR(CCSBAR))
        addi    r6, r6, LO(M85XX_LBCDLLSR(CCSBAR))
        lwz     r3, 0(r6)
	andi.   r3, r3, 0x7ff

	/* Start loop which terminates after ten cycles */
	li      r4, 11
retestLbcDll:
	addi    r4, r4, -1
	cmpwi   r4, 0

	/* terminate loop and generate check stop */
	beq     checkStop   
	/* Delay not more than 2500 CCB clock cycles */ 
	li      r5, 2000
	mtctr   r5
lbcDllDelay:
	bdnz    lbcDllDelay

	/* Read latest tap value */
        lwz     r8, 0(r6)
	andi.   r5, r8, 0x7ff

	/* diff between previous value */
	subf    r7, r5, r3
	/* Move latest value to previous */
	mr      r3, r5