config.h

Freescale MPC85xx BSP (8555/8541)。绝对可用的。

/* config.h - Freescale MPC85xx BSP (8555/8541) configuration file */

/*
 * Copyright 2001-2005 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

#include "copyright_wrs.h"

/*
modification history
--------------------
01d,26apr05,kab  Doc fixes (SPR 108364)
01c,22apr05,dtr  Set CACHE_SNOOP_ENABLE by default - SPR 107990.
01c,14jun05,pcm  removed INCLUDE_DOSFS
01b,15nov04,jln  Support TFFS, PCI 1/2
01a,10sep04,jln  Modify from ads85xx/config.h/01q
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "2.0"
#define BSP_REV         "/0"
           
/* Define Clock Speed and source  */

#define	FREQ_33_MHZ	 33333333
#define	FREQ_66_MHZ	 66666666
#define	FREQ_100_MHZ	 99999999
#define	FREQ_133_MHZ	133333333
#define	FREQ_266_MHZ	266666666

/* only 33Mhz is verified in CDS REVC board */ 

#define	OSCILLATOR_FREQ	FREQ_33_MHZ
#define DEFAULT_SYSCLKFREQ FREQ_266_MHZ
#undef FORCE_DEFAULT_FREQ /* Use to force freq used with DUART/Timers etc */

/* This value is the 60x bus-assigned SDRAM Refresh Timer PSRT setting */
#define	LSRT_VALUE	0x20

/*
 * This value is the setting for the MPTPR[PTP] Refresh timer prescaler.
 * The value is dependent on the OSCILLATOR_FREQ value.  For other values
 * a conditionally compiled term must be created here for that OSCILLATOR_FREQ
 * value.
 *
 * BRGCLK_DIV_FACTOR
 * Baud Rate Generator division factor - 0 for division by 1
 *					 1 for division by 16
 */

#define	DIV_FACT_1	0
#define	DIV_FACT_16	1

/* Fix me:
 * Assume Worst case of 333MHz CCB with local bus clk ratio of 4 
 * ie revA board settings  
 */

#define	TPR			0x2000
#define BRGCLK_DIV_FACTOR	DIV_FACT_16

#define M8260_BRGC_DIVISOR	BRGCLK_DIV_FACTOR

#include "configAll.h"

#include "cds85xx.h"

#define WDT_RATE_MIN         (sysTimerClkFreq / (1 << 29))
#define WDT_RATE_MAX         (sysTimerClkFreq / (1 << 21))

#define DEFAULT_BOOT_LINE \
"mottsec(0,0)host:/wind/river/target/config/cds85xx/vxWorks h=192.168.24.1 e=192.168.24.101 u=demo"

/* MMU and CACHE */

#define INCLUDE_MMU_BASIC
#define USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE



#undef E500_L1_PARITY_RECOVERY

#ifdef E500_L1_PARITY_RECOVERY
  /* *** NOTE FOR PROJECT FACILITY USERS ***
   * Needs to use WRITETHROUGH, building with Project Facility must also
   * change USER_D_CACHE_MODE and USER_I_CACHE_MODE in Project Facility.
   */

# define CACHE_LIBRARY_MODE     CACHE_WRITETHROUGH
# define CAM_DRAM_CACHE_MODE    _MMU_TLB_ATTR_W
# define TLB_CACHE_MODE         VM_STATE_CACHEABLE_WRITETHROUGH

#else  /* E500_L1_PARITY_RECOVERY */

# define CACHE_LIBRARY_MODE     (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)
# define CAM_DRAM_CACHE_MODE    _MMU_TLB_ATTR_M
# define TLB_CACHE_MODE         VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
#endif

#define INCLUDE_CACHE_SUPPORT 
#define USER_D_CACHE_ENABLE
#undef  USER_D_CACHE_MODE
#define USER_D_CACHE_MODE  (CACHE_LIBRARY_MODE)
#define USER_I_CACHE_ENABLE
#undef  USER_I_CACHE_MODE
#define USER_I_CACHE_MODE (CACHE_LIBRARY_MODE)

#define  INCLUDE_L2_CACHE
#undef   INCLUDE_L2_SRAM



  /* If E500_L1_PARITY_RECOVERY is not efined, use local BSP handler.
   * Works for L1 instr cache but not data cache.  Writethrough not needed.
   */  
#ifdef E500_L1_PARITY_RECOVERY

# if defined(INCLUDE_CACHE_SUPPORT) && defined(USER_I_CACHE_ENABLE)
#   if (defined(_WRS_VXWORKS_MAJOR) && (_WRS_VXWORKS_MAJOR >= 6))
#     define INCLUDE_L1_IPARITY_HDLR              /* VxWorks 6.x */
#   else  /* _WRS_VXWORKS_MAJOR */
#     define INCLUDE_L1_IPARITY_HDLR_INBSP        /* VxWorks 5.5.x */
#   endif /* _WRS_VXWORKS_MAJOR */
# endif  /* INCLUDE_CACHE_SUPPORT && USER_I_CACHE_ENABLE */

#endif  /* E500_L1_PARITY_RECOVERY */

#define INCLUDE_BRANCH_PREDICTION

#if ((defined(INCLUDE_L2_CACHE)) && (defined(INCLUDE_L2_SRAM)))
#define L2_CACHE_SIZE      L2SIZ_128KB
#define L2_SRAM_SIZE       L2SIZ_128KB
#elif ((defined(INCLUDE_L2_CACHE)) && (!defined(INCLUDE_L2_SRAM)))
#define L2_CACHE_SIZE      L2SIZ_256KB
#define L2_SRAM_SIZE       0         /* Not Used */
#else
#define L2_SRAM_SIZE       L2SIZ_256KB
#define L2_CACHE_SIZE      0         /* Not Used */
#endif

#define L2SRAM_ADDR        0x7FFC0000
#define L2SRAM_WINDOW_SIZE 0x40000 

#ifdef INCLUDE_NFS
/* Default NFS parameters - constants may be changed here, variables
 * may be changed in usrConfig.c at the point where NFS is included.
 */
#define NFS_USER_ID             2001            /* dummy nfs user id */
#define NFS_GROUP_ID            100             /* dummy nfs user group id */
#define NFS_MAXPATH             255             /* max. file path length */
#endif /* INCLUDE_NFS */

/* Disable Support for SPE 64bit registers */

#define INCLUDE_SPE

/* TSEC is included */

#define INCLUDE_MOT_TSEC_END

#ifdef INCLUDE_MOT_TSEC_END
#define INCLUDE_PRIMARY_TSEC_END
#define INCLUDE_SECONDARY_TSEC_END    
#define INCLUDE_END                   
#endif /* INCLUDE_MOT_TSEC_END */

/* console is always DUART */

#define INCLUDE_DUART

/* Serial channel and TTY */

#if defined(INCLUDE_DUART) 
#  undef  NUM_TTY
#  define NUM_TTY 1
#endif /* INCLUDE_DUART */

/* CPM is not supported */

#undef INCLUDE_CPM

#ifdef INCLUDE_CPM
# undef INCLUDE_MOTFCCEND
# undef INCLUDE_MOT_FCC_END
#endif /* INCLUDE_CPM */

/* MOT FCC not supported yet */

#undef INCLUDE_MOTFCCEND

#ifdef INCLUDE_MOTFCCEND
#ifndef INCLUDE_END
#   define INCLUDE_END                  /* only END-style driver for FCC */
#endif /* INCLUDE_END */
#undef INCLUDE_PRIMARY_FCC_END    /* FCC2 */
#undef INCLUDE_SECONDARY_FCC_END  /* FCC3 */
#endif /* INCLUDE_MOTFCCEND */

/* Optional timestamp support */

#define	INCLUDE_TIMESTAMP
#define	INCLUDE_AUX_CLK

/* Clock rates */

#define	SYS_CLK_RATE_MIN	1	/* minimum system clock rate */
#define	SYS_CLK_RATE_MAX	8000	/* maximum system clock rate */
#define	AUX_CLK_RATE_MIN	1	/* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX	8000	/* maximum auxiliary clock rate */

/* TrueFFS flash support */

#undef INCLUDE_TFFS

#ifdef  INCLUDE_TFFS
#define INCLUDE_SHOW_ROUTINES	/* show routines for system facilities*/
#endif  /* INCLUDE_TFFS */

/* PCI support */

#define  INCLUDE_PCI               /* include PCI library support */

#ifdef  INCLUDE_PCI

#define INCLUDE_PCI_AUTOCONF
#define EPIC_EX_DFT_POLAR	EPIC_INT_ACT_LOW

#define CDS85XX_PCI_1_BUS       1
#define CDS85XX_PCI_2_BUS       2

/* define this MACRO to enable PCI 2 */

#undef  INCLUDE_CDS85XX_SECONDARY_PCI

/*  cds85xx support dual PCI controllers */

/*
********************************************
   CPU Addr                                         PCI Addr ( PCI1 or PCI2)


PCI_LOCAL_MEM_BUS        -------------------------- PCI_MSTR_MEM_BUS
                         -                        - 
                         -                        -
PCI_LOCAL_MEM_BUS +      -------------------------- PCI_MSTR_MEM_BUS +
PCI_LOCAL_MEM_SIZE       -                        - PCI_MSTR_MEM_SIZE
                         -                        - 
                         -                        ----- PCI Bridge (for PCI1 only)
                         -                        -     configuration regs
                         -                        - 
CPU_PCI_MEM_ADRS  (PCI1) -------------------------- PCI_MEM_ADRS
CPU_PCI_MEM_ADRS2 (PCI2) -                        - PCI_MEM_ADRS2
                         -                        - 
CPU_PCI_MEMIO_ADRS       -------------------------- PCI_MEMIO_ADRS
CPU_PCI_MEMIO_ADRS2      -                        - PCI_MEMIO_ADRS2
                         -                        - 
CPU_PCI_IO_ADRS  (PCI1)  -------------------------- PCI_IO_ADRS