target.ref

Freescale MPC85xx BSP (8555/8541)。绝对可用的。

	m85xxTimer.c - timer driver
	mot85xxPci.c - On-chip PCI Bridge library/interrupt handler.
	sysEpic.c - On chip interrupt controller
	motTsecEnd.c - TSEC ethernet controller
	ns16553Sio.c - serial driver
	miiLib.c - Media Independent Interface library
	mem/byteNvRam.c - nvram driver
        gei82543End.c - Intel 8254x Gigabit controller
        sysL2Cache.c - L2 cache library
        mot85xxPci.c - PCI initialization library
        sysBusPci.c - prepare PCI auto configuration library

\sh Memory Maps


The following table describes the cds85xx default memory map:
\ts

Start | Size | End | Access to
------------------------------
0x0000_0000 | 512MB | 0x1FFF_FFFF | DDR SDRAM
0x5000_0000 | 64MB | 0x53FF_FFFF | PCI 1 Prefetchable Memory
0x5400_0000 | 64MB | 0x57FF_FFFF | PCI 1 Non-Prefetchable Memory
0x5800_0000 | 64MB | 0x5BFF_FFFF | PCI 1 IO 
0x6000_0000 | 64MB | 0x63FF_FFFF | PCI 2 Prefetchable Memory
0x6400_0000 | 64MB | 0x67FF_FFFF | PCI 2 Non-Prefetchable Memory
0x6800_0000 | 64MB | 0x6BFF_FFFF | PCI 2 IO 
0xF700_0000 | 16MB | 0xF7FF_FFFF | NVRAM/CADMUS
0xF800_0000 | 64MB | 0xFBFF_FFFF | LBC SDRAM
0xFE00_0000 | 1MB | 0xFE0F_FFFF | Configuration Control Registers
0xFF00_0000 | 8MB | 0xFF7F_FFFF | Flash 2
0xFF80_0000 | 8MB | 0xFFFF_FFFF | Flash 1
\te



The following table describes the default VxWorks macros which
are used to address memory
\ts

Macro Name | Macro Definition | Description
------------------------------
LOCAL_MEM_LOCAL_ADRS | 0x0000_0000 | Base of RAM
RAM_LOW_ADRST | LOCAL_MEM_LOCAL_ADRS + 0x0001_0000 | VxWorks image loaded here. Stack grows down from this address.
RAM_HIGH_ADRS | LOCAL_MEM_LOCAL_ADRS + 0x00d0_0000 | VxWorks bootrom loaded here.
LOCAL_MEM_SIZE | 1000_0000 | Default 256 MBytes of RAM
ROM_BASE_ADRS | 0xFFF0_0000 | Base address of ROM
ROM_TEXT_ADRS | ROM_BASE_ADRS + 0x100 | Text must start after vector table 
ROM_WARM_ADRS | ROM_TEXT_ADRS + 8 | Warm Reboot Entry Address
ROM_SIZE | 0x0010_0000 | Default 1 MByte of ROM
\te


\sh Support for L2 Cache
L2 Cache is configured with callback function
pointers for L2 cache Global Invalidation, L2 Cache Enable, L2 Cache
Flush and L2 Cache Disable are initialized in sysHwInit().  By default, the
256 KB L2 is configured to 256 KB of cache. If a different configuration is 
desired, a new bootrom image should be used to match the RAM image 
configuration of L2.

\sh Operating Speed
The processor has built-in PLL circuits to control the operating speed of 
the Core Complex Bus (CCB) as well as the E500 core. The BSP supports both
266MHz and 333MHz for CCB. The maximum clock rate for E500 core could be up 
to 833MHz for MPC8541. Please check the SW3 switch of the CPU card for 
detail.

\cs
     CCBPLL ratio  |  SW3[5:8] |   CCB freq
     ----------------------------------------
     |  8:1        |   1000    |   266MHz   |
     ----------------------------------------
     | 10:1        |   1010    |   333MHz   |
     ----------------------------------------
\ce

\cs

     CPUPLL ratio  |  SW3[3:4]  |  CORE freq
     ----------------------------------------
     |  2:1        |    00      | 2   * CCB |
     |  5:2        |    01      | 2.5 * CCB |
     |  3:1        |    10      | 3   * CCB |
     |  7:2        |    11      | 3.5 * CCB |
     ---------------------------------------
\ce

\sh Booting
Upon reset, the MPC85xx begins executing from 0xFFFF_FFFC. Only the last
4KB of memory is mapped by the TLB.  The instruction at 0xFFFF_FFFC branches
to resetEntry() located at the last 2KB of memory to begin initialization
and mapping of memory static TLB entries.  The DDR SDRAM is then mapped to
0x0 where the vectors are setup to use and execution is then transferred
to the RAM after copying and uncompressing if necessary.

The bootrom for the cds85xx allows loading vxWorks with two TSEC ethernet 
channels. In the boot dialog, they correspond to the "mottsec0" and
the "mottsec1" devices. To switch between the two boot devices after a load
is attempted, a hard reset or power cycle is necessary in order for the 
device to function properly.  After the reset, press a key to stop the 
countdown, then use the "c" command to change the boot device to the desired 
network device.

The cds85xx bootrom also supports loading vxWorks by using Intel 8254x Gigabit
Ethernet controller. A Intel 82546/82545/82544/82543/82540 based NIC could be 
plugged into an empty PCI slot. The config.h need to be modified to define 
INCLUDED_PCI and INCLUDED_GEI8254X_END. If the 8254x NIC is plugged into the 
PCI slot on the CPU card, the INCLUDE_CDS85XX_SECONDARY_PCI also need to be 
defined. Rebuild the bootrom with above changes in the config.h. Reflash the 
bootrom to the flash. The boot device is "gei" for Intel 8254X gigabit 
controllers.

The cds85xx bootrom can also load the vxWorks image located in the flash 
via TFFS. To include TFFS, define the INCLUDE_TFFS in the config.h. 
By default, the flash address FF800000 - FFEFFFFF (7MB) is configured to the 
primary TFFS. To configure the flash FF000000 - FF6FFFFFF (7MB) as the 
secondary TFFS, INCLUDE_CDS85XX_SECOND_TFFS_FLASH also needs to be defined. 
Rebuild and reflash the new bootrom with TFFS. The boot device is "tffs=0,0" 
for the primary flash, and "tffs=1,0" for the secondary flash. The vxWorks 
images need to be copied into the TFFS before booting.

\sh DDR RAM Size
This BSP can support up to 512MB DDR memory. By default, only 256MB DDR
memory is configured in the config.h. Change the definition of LOCAL_MEM_SIZE
for desired DDR memory size.

\sh Local Bus SDRAM Size
Initial boards and BSP are supplied with a 64MB SDRAM.

\sh  NVRAM Support 
This BSP uses NvRam on the 8KB Maxim DS1533WP RTC/NVRAM device. The bootline 
is stored at the beginning of the NvRam. The last 16-byte is for the RTC device.
The actual NVRAM size is (8 * 1024 - 16) = 8176 bytes.

\sh Network Configuration
The TSEC port allows 10/100/1000T connection. The driver will auto-negotiate and 
configure the port accordingly. The BSP also supports Intel 82546/82545/82544/
82540/82543 based NICs. The FCC ports are not supported in this release. 

\sh ROM Considerations
bootrom.hex is provided with this BSP. The bootrom is configured to 
a ROM base address of 0x0. When programming the bootrom to the FLASH an offset
of 0xFFF00000 need to be given.

\sh BOOT FLASH
There are two flash banks on the cds85xx board. By default, if the carrier 
card's SW2[12]=01, UBOOT would start the system. This BSP would program the 
bootrom into the flash bank with Carrier Card's SW2[12]=00. The SW2[12] is used
to swap the flash bank for booting.

\sh PCI Support

There are two PCI host controllers on MPC8555/MPC8541, both are compliant to PCI 2.2.
In the CDS85XX reference board, the primary PCI (PCI1) interface is via the Carrier 
edge fingers, and the secondary PCI (PCI2) interface is via the CPU card's right angle 
slot. The CDS reference board has ability to partition the 64-bit interface into two 
32-bit PCI interfaces, PCI1 and PCI2. The PCI 1 64-bit configuration has now been 
tested in this release.

The CPU card's SW1[7] should be set to 1 to use the SYSCLK for PCI1 clock, and 
the SW1[8] should be 0 to use PCICLK for PCI2 clock.  

The cds85xx BSP by default uses the PCI auto configuration library to only configure 
the PCI devices on the PCI bus 0 for both PCI 1 and PCI 2. Any PCI device
plugged in the PCI slot on the Arcadia board (base board) is in the bus 0 of the 
primary PCI (PCI 1). Other devices on the Arcadia board such as Floppy/Harddisk 
controllers, Keyboard/Mouse controllers, etc are on the PCI bus 0, and they are NOT 
supported.

To use the secondary PCI interface (PCI 2), the INCLUDE_CDS85XX_SECONDARY_PCI should be 
defined in config.h, and the CPU card's SW2[8] should be "off".

The Intel 8254x Gigabit Ethernet controllers are the only PCI devices supported in 
this release. Define INCLUDE_GEI8254X_END in config.h to enable this device, and define
INCLUDE_SECONDARY_GEI_END if you have two Intel 8254x devices on the PCI interfaces.

Since there are two separate PCI host controllers in the cds85xx board, it is necessary
to distinguish the PCI 1 and PCI 2 before PCI configuration cycles are issued. To enable
the PCI 1 configuration, sysPciConfigEnable(1) needs to be called first, for example:

\cs
   /@ to show the header of the PCI device on bus 0, device number 20, and 
    * function number 0 of the PCI 1 
    @/

   ->sysPciConfigEnable 1
   ->pciHeaderShow 0, 20, 0

\ce

To enable the PCI 2 configuration, sysPciConfigEnable(2) should be involved first:

\cs
   /@ to show the header of the PCI device on bus 0, device number 20, and 
    * function number 0 of the PCI 2 
    @/

   ->sysPciConfigEnable 2
   ->pciHeaderShow 0, 21, 0

\ce

\sh TrueFFS
TrueFFS is an optional product to use a flash device as a file system.
To use TrueFFS, define INCLUDE_TFFS in config.h. To configure the secondary
flash (0xFF000000 - 0xFF6FFFFF) as another TFFS, INCLUDE_CDS85XX_SECOND_TFFS_FLASH 
also needs to be defined in config.h.

There are two flash banks on the cds85xx board. Each has 8 Mbytes with last 1 MByte 
for the bootloader. One contains UBOOT, the other is vxWorks's bootrom. This 
layout allows each flash has 7 MByte ready for TFFS. 

To initialize and format the primary flash device (FFF00000 - FFEFFFFF) for TFFS,
run the following commands in the shell:
\cs
    ->sysTffsFormat (0);
\ce

To initialize and format the secondary flash (FF00000 - FF6FFFFF)for TFFS, 
run the following commands in the shell:

\cs
   ->sysTffsFormat (1);
\ce

The above commands will take a few minutes to complete.  Do not
interrupt the board during this time or risk damaging the flash.
Properly formatted TFFS volumes can be mounted for use using the 
following commands each time vxWorks boots:

\cs
    /@ for primary flash @/
    usrTffsConfig (0, 0, "/tffs0/");
    /@ for secondary flash @/
    usrTffsConfig (1, 0, "/tffs1/");
\ce

TrueFFS can also serve as a boot device.  Assuming the target 
is configured to access files on the host file system, the 
following command will copy vxWorks from the host to the TFFS 
volume on the target.  Substitute /tff1/ for the secondary flash:

\cs
    copy ("vxWorks.st", "/tffs0/vxWorks.st");
\ce

To boot with a vxWorks image in the TFFS volume, build a bootrom
with INCLUDE_TFFS defined in config.h.  Program the new bootrom 
image into the boot flash and specify the following in the 
boot dialog:

\cs
    /@ for primary flash @/
    boot device: tffs=0,0
    file name  : /tffs0/vxWorks.st
    /@ for secondary flash @/
    boot device: tffs=1,0
    file name  : /tffs1/vxWorks.st
\ce

However, in this release, we don't support using TFFS utility routines 
to program the bootrom. 

\sh Serial Configuration
The UART device is configured with 8 data bits, 1 stop bit, hardware
handshaking, and parity disabled.  They operate at 9600 bps. The
on-chip DUART on the MPC8541 and MPC8555 is supported. However, only 
the second channel of the DUART is used on the cds85xx reference boards.

\sh Programmable Interrupt Controller
The PIC driver provided by this BSP supports all internal and external
interrupt sources.  It can also be configured to route such sources to
the critical interrupt pin, as well as acting as handling the critical
interrupts.  However, since critical interrupts are routed directly to
the interrupt source instead of being manager by the PIC with IACK or
EOI, the Critical Interrupt Summary registers are used to check for the
source.  The transient values in these registers causes spurious vector
when indexing into the vector table.

SPECIAL CONSIDERATIONS
This section describes miscellaneous information that the user needs
to know about the BSP.

\sh Delivered Objects
\is
\i bootrom

\i bootrom_uncmp.hex

\i bootrom_uncmp.bin

\i vxWorks

\i vxWorks.sym

\i vxWorks.st
\ie


\sh Silicon Consideration

A Tornado 2.2.1 OS patch is required for CPU errata #29.
You should ensure the patch for SPR 99776 is installed if you enable the 
instruction MMU.

KNOWN PROBLEMS

\sh Bootrom does not boot when build with GNU in Tornado 2.2.1
Tornado 2.2.1 contains a GNU makefile with missing lines.  The file is
$WIND_BASE/target/h/tool/gnu/make.PPC85XXgnu.  To verify the problem,
run "objdumpppc --headers rom_image_name" and check the .reset section.
If it does not end in 0xfffc, it is likely due to this problem.  (SPR#94153)

To correct this problem, add the following lines just before "TOOLENV = ppc"
near the end of make.PPC85XXgnu and rebuild the bootrom:

\cs
LD_SCRIPT_RAM   = -defsym wrs_kernel_rom_size=0x0$(ROM_SIZE) \
                  -T $(TGT_DIR)/h/tool/gnu/ldscripts/link.DOTBOOTRAM
LD_SCRIPT_ROM   = -defsym wrs_kernel_rom_size=0x0$(ROM_SIZE) \
                  -T $(TGT_DIR)/h/tool/gnu/ldscripts/link.DOTBOOTROM
\ce

BIBLIOGRAPHY
Please refer to the following documents for further information on the
cds85xx boards.

\tb MPC8555E PowerQuiccIII Integrated Communications Processor Reference Manual 

\tb PowerPC E500 Core Complex reference Manual 

\tb Motorola PowerPC Microprocessor Family: The Programming Environments 

\tb CDS Carrier User's Manual 

\tb CDS CPUCard User's Manual 

\tb Arcadia RapidIo Hardware Interoperability Platform Design Workbook 

\tb CDS Quick Start-Up Guide .