hwctl_mx31.cpp

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
// hwctl_mx31.cpp
//
//
// Description: Device-specific controls for ATAPI hardware on i.MX31 ADS
//

#include <atamain.h>
#include <bsp.h>

//static PCSP_ATA_REG g_pVAtaReg = NULL;
//static PCSP_PBC_REGS g_pPBC = NULL;

BOOL AtapiDeviceInit()
{   
#if 0
    PHYSICAL_ADDRESS phyAddr;

    phyAddr.QuadPart = BSP_BASE_REG_PA_PBC_BASE;
    g_pPBC = (PCSP_PBC_REGS) MmMapIoSpace(phyAddr, sizeof(CSP_PBC_REGS), FALSE);
    if (g_pPBC == NULL)
    {
        RETAILMSG(1, (TEXT("ATA:  MmMapIoSpace failed!\r\n")));
    }

    phyAddr.QuadPart = CSP_BASE_REG_PA_ATA_CTRL;
    // Map peripheral physical address to virtual address
    g_pVAtaReg = (PCSP_ATA_REG) MmMapIoSpace(phyAddr, sizeof(CSP_ATA_REG), FALSE);

    return (g_pVAtaReg != NULL);
#else
    return TRUE;
#endif
}

BOOL AtapiDeviceDeinit()
{
#if 0
    if (g_pVAtaReg != NULL)
    {
        MmUnmapIoSpace(g_pVAtaReg, sizeof(CSP_ATA_REG));
        g_pVAtaReg = NULL;
    }
    if (g_pPBC != NULL)
    {
        MmUnmapIoSpace(g_pPBC, sizeof(CSP_PBC_REGS));
        g_pPBC = NULL;
    }
#endif

    return TRUE;
}

BOOL AtapiDeviceIsPowerSupported()
{
    return FALSE; // TODO: Is it? Maybe through MC13783?
}

BOOL AtapiDeviceIsHardResetSupported()
{
    return FALSE; // don't need hard reset for now
}

void AtapiDeviceSetPower(BOOL bOn)
{

    return;

    if(bOn)
    {
        DDKClockSetGatingMode(DDK_CLOCK_GATE_INDEX_ATA, DDK_CLOCK_GATE_MODE_ENABLED_ALL);
#if 0
        // 0. Assume RESET is asserted (may not hurt to re-assert RESET)
        AtapiDeviceSetHardReset(TRUE);

        // 1. Enable HDD power
        // TODO: GIO_setBit(GIO_HDD_POWER);

        // 2. Sleep() for power stabilization.  NOTE:  This is variable, dependent on each OEM's
        // hardware implementation.  Must design to spec, not measured.
        Sleep(2);

        // 3. Enable HDD output buffer enable
        // TODO: GIO_setBit(GIO_HDD_OE);

        // 4. Sleep() 25 usec for ATAPI RESET assertion requirements.  Make it 1msec to be safe.
        Sleep(1);

        // 5. Negate RESET.
        AtapiDeviceSetHardReset(FALSE);

        // 6. Sleep() 2 msec before reading the ATAPI BSY bit.  This is an ATAPI requirement.
        Sleep(2);
#endif
    }
    else
    {
#if 0
        // 1. Assert RESET, Disable HDD output buffer eanble, Disable HDD power SIMULTANEOUSLY (no sleep()s needed)
        AtapiDeviceSetHardReset(TRUE);  
        // TODO: GIO_clearBit(GIO_HDD_OE);
        // TODO: GIO_clearBit(GIO_HDD_POWER);
#endif
        DDKClockSetGatingMode(DDK_CLOCK_GATE_INDEX_ATA, DDK_CLOCK_GATE_MODE_DISABLED);
    }

}

void AtapiDeviceSetHardReset(BOOL bAsserted)
{    

#if 0
    if(bAsserted)
    {
        // Reset the HDD
        OUTREG32(&g_pVAtaReg->ATAControl, 0x00); // Clear fifo_rst_b and ata_rst_b (TODO: Define ATA register bit fields)
    }
    else
    {
        // Take the HDD out of reset
        OUTREG32(&g_pVAtaReg->ATAControl, 0x40); // Clear fifo_rst_b and set ata_rst_b (TODO: Define ATA register bit fields)
    }
#endif

}