sdc.c

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

    // NOTE: this takes care of the upper four bits in the FH field
    OUTREG32(&g_pIPU->IPU_IMA_DATA, ((height - 1) >> 8));


    //=================================
    // Configure Second 132 bit word
    //=================================
    //..skip over EBA0 and EBA1
    //.. Set IPU_IMA_ADDR (IPU Internal Memory Access Address)
    OUTREG32(&g_pIPU->IPU_IMA_ADDR,
            CSP_BITFVAL( IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |
            CSP_BITFVAL( IPU_IPU_IMA_ADDR_ROW_NU, (2 * channel + 1))|
            CSP_BITFVAL( IPU_IPU_IMA_ADDR_WORD_NU, 2));

    //...2nd 32 bit word

    // Default access type to 32-bit
    sat_code = 2;

    switch (bpp)
    {
        case 32:
            bpp_code = 0;
            npb_code = 8-1;
            ofs[0] = 0;
            ofs[1] = 8;
            ofs[2] = 16;
            ofs[3] = 24;
            wid[0] = 8-1;
            wid[1] = 8-1;
            wid[2] = 8-1;
            wid[3] = 8-1;
            break;

        case 24:
            bpp_code = 1;
            npb_code = 10-1;
            sat_code = 0;
            ofs[0] = 0;
            ofs[1] = 8;
            ofs[2] = 16;
            ofs[3] = 0;
            wid[0] = 8-1;
            wid[1] = 8-1;
            wid[2] = 8-1;
            wid[3] = 0;
            break;

        case 16:
            bpp_code = 2;
            npb_code = 16-1;
            ofs[0] = 0;
            ofs[1] = 5;
            ofs[2] = 11;
            ofs[3] = 0;
            wid[0] = 5-1;
            wid[1] = 6-1;
            wid[2] = 5-1;
            wid[3] = 0;
            break;

        case 8:
            bpp_code = 3;
            npb_code = 32-1;
            ofs[0] = 0;
            ofs[1] = 0;
            ofs[2] = 0;
            ofs[3] = 0;
            wid[0] = 8-1;
            wid[1] = 0;
            wid[2] = 0;
            wid[3] = 0;
            break;

        case 4:
            bpp_code = 4;
            npb_code = 32-1;
            ofs[0] = 0;
            ofs[1] = 0;
            ofs[2] = 0;
            ofs[3] = 0;
            wid[0] = 4-1;
            wid[1] = 0;
            wid[2] = 0;
            wid[3] = 0;
            break;

        case 1:
            bpp_code = 5;
            npb_code = 64-1;
            ofs[0] = 0;
            ofs[1] = 0;
            ofs[2] = 0;
            ofs[3] = 0;
            wid[0] = 1-1;
            wid[1] = 0;
            wid[2] = 0;
            wid[3] = 0;
            break;

        default:
            bpp_code = 7;
        // TODO:  Should report error here.  bpp_code is reserved.
        break;
    }

    bam_code = vFlip ? 1 : 0;

    // - BPP [2:0], SL [16:3], PFS [19:17], BAM [24:20], NPB [30:25],
    // - RESERVED [31]
    // - Set BPP to 24bpp (1)
    // - Set SL (Scaling Factor) to bytes_pp * width
    // - Set PFS (Packing) to RGB (%100)
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_BPP, bpp_code)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SL, (stride - 1))|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_PFS, 0x4)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_BAM, bam_code)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_NPB, npb_code));

    //...3rd 32 bit word
    // SAT [1:0], SCC [2], OFS0 [7:3], 0FS1 [12:8], OFS2 [17:13], OFS3 [22:18]
    // - WID0 [25:23], WID1 [28:26], WID2 [31:29]
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SAT, sat_code)|
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_SCC, 0)|

                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS0, ofs[0]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS1, ofs[1]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS2, ofs[2]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_OFS3, ofs[3]) |

                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID0, wid[0]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID1, wid[1]) |
                CSP_BITFVAL( IPU_IPU_IMA_DATA_PARAM_WID2, wid[2]));

    //...4th 32 bit word
    // WID3 [2:0], DEC_SEL [3],
    // Set WID3 (7 - 8 bit size), Color component 3 width (Alpha)
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
                CSP_BITFVAL(IPU_IPU_IMA_DATA_PARAM_WID3, wid[3]));

    // Cede control of IPU_IMA registers by writing 0 to IPU_IMA_ADDR
    OUTREG32(&g_pIPU->IPU_IMA_ADDR, 0);
}

//------------------------------------------------------------------------------
//
// Function: SetSrcBuffer
//
// Set the buffer for Init the IPU DMA module
//
// Parameters:
//      None.
//
// Returns:
//      None.
//------------------------------------------------------------------------------
static void SetSrcBuffer(int channel, PHYSICAL_ADDRESS *pAddr, DISP_BUF_TYPE bufNum)
{
    UINT32 wordNo = (bufNum == eBUF_0) ? 0 : 1;
    UINT32 oldVal, newVal;

    // Set IPU_IMA_ADDR (IPU Internal Memory Access Address)
    newVal = CSP_BITFVAL(IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |
            CSP_BITFVAL(IPU_IPU_IMA_ADDR_ROW_NU, (2 * channel + 1))|
            CSP_BITFVAL(IPU_IPU_IMA_ADDR_WORD_NU, wordNo);

    while (1)
    {
        oldVal = INREG32(&g_pIPU->IPU_IMA_ADDR);
        if (oldVal == 0)
        {
            // Try to set IPU_IMA registers.
            if (InterlockedTestExchange(&g_pIPU->IPU_IMA_ADDR,
                oldVal, newVal) == oldVal)
            {
                // Successfully set IMA_ADDR.
                break;
            }
        }
        // IPU_IMA controlled by another process.
        // Surrender CPU and then try again.
        Sleep(0);
    }

    //..Set buffer to physical frame buffer address
    OUTREG32(&g_pIPU->IPU_IMA_DATA, (unsigned int) pAddr->QuadPart);

    // Cede control of IPU_IMA registers by writing 0 to IPU_IMA_ADDR
    OUTREG32(&g_pIPU->IPU_IMA_ADDR, 0);
}


//------------------------------------------------------------------------------
//
// Function: ForegroundWindowConfig
//
// Configure the foreground plane in the SDC.
//
// Parameters:
//      width
//          [in] Width of the foreground plane display area.
//
//      height
//          [in] Height of the foreground plane display area.
//
//      bpp
//          [in] BPP of foreground plane image for display.
//
// TODO: Support
//      verticalFlip
//          [in] Boolean indicating whether the displayed image
//          is vertically flipped.
//
// TODO: Support
//      alpha
//          [in] Alpha blending factor for  the graphics plane (indicated by the
//          plane parameter).  The following equation determines the output
//          pixel color:
//              OP = IGP * x + IVP * (1 - x)
//              where OP = Output Pixel
//                    IGP = Input Graphics Pixel
//                    IVP = Input Video Pixel
//                    x = (alpha + floor(alpha/128))/256
//
//      colorKey
//          [in] Color key for the graphics plane, indicated by the plane parameter.
//
//      plane
//          [in] Value indicating whether Plane 1 or Plane 0 should be
//          marked as the graphics (foreground) plane.
//
//
// Returns:
//      TRUE if success; FALSE if failure.
//------------------------------------------------------------------------------
BOOL ForegroundWindowConfig(PDISPLAY_SDC_FG_CONFIG_DATA pDispConfigData)
{
    UINT32 graphWindCtrl;
    UINT32 RGBColorKey;

    // Convert Microsoft color key mask into the one of the IPU
    // for graphic window.
    // Microsoft : r bit 0~7; g bit 8~15; b bit 16~23
    // IPU:        r bit 16~23; g bit 8~15, b bit 0~7
    switch (pDispConfigData->bpp)
    {
        // TODO: Support non-16BPP pixel formats
        case 16:
            RGBColorKey =
                (((pDispConfigData->colorKey & 0x001F) << (IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_R_LSH+3)) |
                ((pDispConfigData->colorKey & 0x07E0) << (IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_G_LSH-5+2)) |
                ((pDispConfigData->colorKey & 0xF800) >> (11-IPU_SDC_GRAPH_WIND_CTRL_SDC_KEY_COLOR_B_LSH-3)));
            break;
        default:
            RGBColorKey = 0;
            break;
    }

    // Build value for graphics window control and write it to register
    pDispConfigData->alpha = 0xFF;
    graphWindCtrl = (pDispConfigData->alpha << 24) | RGBColorKey;
    OUTREG32(&g_pIPU->SDC_GRAPH_WIND_CTRL, graphWindCtrl);
    INSREG32BF(&g_pIPU->SDC_COM_CONF, IPU_SDC_COM_CONF_GWSEL, pDispConfigData->plane);
    if (pDispConfigData->colorKey != 0xFFFFFFFF)
    {
        INSREG32BF(&g_pIPU->SDC_COM_CONF, IPU_SDC_COM_CONF_SDC_KEY_COLOR_EN,
            IPU_ENABLE);
    }
    else
    {
        INSREG32BF(&g_pIPU->SDC_COM_CONF, IPU_SDC_COM_CONF_SDC_KEY_COLOR_EN,
            IPU_DISABLE);
    }

    // Determine if we need to crop Foreground window (i.e., change FG width)
    if ((g_iCurrentFGXP + pDispConfigData->width) > g_iXValMax)
    {
        // The foreground width plus FGXP exceeds the maximum, so
        // we must crop the foreground window.
        pDispConfigData->width = g_iXValMax - g_iCurrentFGXP - 1;
    }

    // go set up the IDMA
    _init_dma(pDispConfigData->width, pDispConfigData->height, pDispConfigData->bpp, pDispConfigData->stride, pDispConfigData->verticalFlip, GRAPHICS_DMA_CHANNEL);

    return TRUE;
}


//------------------------------------------------------------------------------
//
// Function: ForegroundWindowSetSrcBuffer
//
// Set up the source buffer in the IPU DMA.  This takes the physical address
// passed as a parameter and configures the DMA to load the image from this
// buffer.
//
// Parameters:
//      pAddr
//          [in] PHYSICAL_ADDRESS for buffer containing frame to display
//          to the foreground plane.
//
//      bufNum
//          [in] Selects buffer 0 or buffer 1 in the DMA.
//
// Returns:
//      None.
//------------------------------------------------------------------------------
void ForegroundWindowSetSrcBuffer(PHYSICAL_ADDRESS *pAddr)
{
    // Set IPU_IMA_ADDR (IPU Internal Memory Access Address)
    if (g_iSDCFGNextBuffer == 0)
    {
        SetSrcBuffer(GRAPHICS_DMA_CHANNEL, pAddr, g_iSDCFGNextBuffer);

        // Set DMA VF Channel 0 ready
        SETREG32(&g_pIPU->IPU_CHA_BUF0_RDY,
                CSP_BITFVAL(IPU_DMA_CHA_DMASDC_1, IPU_DMA_CHA_READY));

        g_iSDCFGNextBuffer = 1;
    }
    else
    {
        SetSrcBuffer(GRAPHICS_DMA_CHANNEL, pAddr, g_iSDCFGNextBuffer);

        // Set DMA VF Channel 1 ready
        SETREG32(&g_pIPU->IPU_CHA_BUF1_RDY,
                CSP_BITFVAL(IPU_DMA_CHA_DMASDC_1, IPU_DMA_CHA_READY));

        g_iSDCFGNextBuffer = 0;
    }

	// Save last address in case we need to restore later.
	g_SDCFGBuf_Saved = (UINT32) pAddr->QuadPart;

}

void ForegroundWindowRestore()
{
	PHYSICAL_ADDRESS phyAddr;