📄 sdc.c
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if (g_hSDCFGIntrEvent == NULL)
{
DEBUGMSG(SDC_ERROR,
(TEXT("%s: CreateEvent for IPU Interrupt failed\r\n"), __WFUNCTION__));
return ret;
}
// One-time creation of g_hIPUBase handle
if (g_hIPUBase == NULL)
{
// open handle to the IPU_BASE driver in order to enable IC module
g_hIPUBase = CreateFile(TEXT("IPU1:"), // "special" file name
GENERIC_READ|GENERIC_WRITE, // desired access
FILE_SHARE_READ|FILE_SHARE_WRITE, // sharing mode
NULL, // security attributes (=NULL)
OPEN_EXISTING, // creation disposition
FILE_FLAG_RANDOM_ACCESS, // flags and attributes
NULL); // template file (ignored)
if (g_hIPUBase == INVALID_HANDLE_VALUE)
{
DEBUGMSG(SDC_ERROR,
(TEXT("%s: Opening IPU_BASE handle failed!\r\n"), __WFUNCTION__));
return ret;
}
}
//----- General configuration
// Set little endian
INSREG32BF(&g_pIPU->IPU_CONF,
IPU_IPU_CONF_PXL_ENDIAN, IPU_LITTLE_ENDIAN);
//----- Display interface configuration
switch(currentPanel -> TYPE)
{
case IPU_PANEL_SHARP_TFT:
//... SDC_COM_CONF
OUTREG32( &g_pIPU->SDC_COM_CONF,
//.. SDC mode
CSP_BITFVAL(IPU_SDC_COM_CONF_SDC_MODE, IPU_SDC_MODE_TFT_COLOR)|
//.. sharp pannel enable
CSP_BITFVAL(IPU_SDC_COM_CONF_SHARP, 0x1)|
//.. dual mode enable
CSP_BITFVAL(IPU_SDC_COM_CONF_DUAL_MODE, 0));
//... SDC_SHARP_CONF_1
OUTREG32( &g_pIPU->SDC_SHARP_CONF_1,
//..cls rise delay
CSP_BITFVAL( IPU_SDC_SHARP_CONF_1_CLS_RISE_DELAY, 0x2)|
//..ps fall delay
CSP_BITFVAL( IPU_SDC_SHARP_CONF_1_PS_FALL_DELAY, 0x1)|
//..rev toggle delay
CSP_BITFVAL( IPU_SDC_SHARP_CONF_1_REV_TOGGLE_DELAY, 0xfd));
//... SDC_SHARP_CONF_2
OUTREG32(&g_pIPU->SDC_SHARP_CONF_2,
//..cls fall delay
CSP_BITFVAL( IPU_SDC_SHARP_CONF_2_CLS_FALL_DELAY, 0xf4)|
//..ps rise delay
CSP_BITFVAL( IPU_SDC_SHARP_CONF_2_PS_RISE_DELAY, 0xf5));
break;
// NEC VGA Driver
case IPU_PANEL_NEC_TFT:
case IPU_TV_NTSC:
case IPU_TV_PAL:
OUTREG32( &g_pIPU->SDC_COM_CONF,
//.. SDC mode
CSP_BITFVAL(IPU_SDC_COM_CONF_SDC_MODE, IPU_SDC_MODE_TFT_COLOR));
break;
default:
DEBUGMSG(SDC_ERROR,
(TEXT("Error configuring IPU SDC. Panel Type is not supported.\r\n Exiting Initialization\r\n")));
return FALSE;
}
switch (currentPanel -> TYPE)
{
case IPU_PANEL_SHARP_TFT:
case IPU_PANEL_NEC_TFT:
//... SDC_HOR_CONF
OUTREG32( &g_pIPU->SDC_HOR_CONF,
//.. display width for tearing and Vsync calculation
CSP_BITFVAL(IPU_SDC_HOR_CONF_SCREEN_WIDTH, (UINT32) (currentPanel -> WIDTH + currentPanel -> HSTARTWIDTH + currentPanel -> HENDWIDTH) ) |
//.. horizontal synchronization pulse
CSP_BITFVAL(IPU_SDC_HOR_CONF_H_SYNC_WIDTH, currentPanel -> HSYNCWIDTH - 1));
//... SDC_VER_CONF
OUTREG32( &g_pIPU->SDC_VER_CONF,
//..line/pixel resolution
CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH_L, 0x1)|
//..display height for tearing and Vsync calculation
CSP_BITFVAL(IPU_SDC_VER_CONF_SCREEN_HEIGHT, (UINT32) (currentPanel -> HEIGHT + currentPanel -> VSTARTWIDTH + currentPanel -> VENDWIDTH) ) |
//..vsync size
CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH, currentPanel -> VSYNCWIDTH));
break;
case IPU_TV_NTSC:
case IPU_TV_PAL:
//... SDC_HOR_CONF
OUTREG32( &g_pIPU->SDC_HOR_CONF,
//.. display width for tearing and Vsync calculation
CSP_BITFVAL(IPU_SDC_HOR_CONF_SCREEN_WIDTH, (UINT32) (currentPanel -> WIDTH + currentPanel -> HSTARTWIDTH + currentPanel -> HENDWIDTH - 1) ) |
//.. horizontal synchronization pulse
CSP_BITFVAL(IPU_SDC_HOR_CONF_H_SYNC_WIDTH, currentPanel -> HSYNCWIDTH - 1));
//... SDC_VER_CONF
OUTREG32( &g_pIPU->SDC_VER_CONF,
//..line/pixel resolution
CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH_L, 0x1)|
//..display height for tearing and Vsync calculation
CSP_BITFVAL(IPU_SDC_VER_CONF_SCREEN_HEIGHT, (UINT32) (currentPanel -> HEIGHT + currentPanel -> VSTARTWIDTH + currentPanel -> VENDWIDTH - 1) ) |
//..vsync size
CSP_BITFVAL(IPU_SDC_VER_CONF_V_SYNC_WIDTH, currentPanel -> VSYNCWIDTH - 1));
break;
}
temp = INREG32(&g_pIPU->DI_DISP_IF_CONF) & 0x78FFFFFF;
//... DI_DISP_IF_CONF
OUTREG32(&g_pIPU->DI_DISP_IF_CONF,
//..data mask
CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_DATAMASK, m_SignalPol.DATAMASK_EN )|
// select interface display clock
CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_CLK_SEL, m_SignalPol.CLKSEL_EN)|
// display clock idle enable
CSP_BITFVAL( IPU_DI_DISP_IF_CONF_DISP3_CLK_IDLE, m_SignalPol.CLKIDLE_EN) |
// Old value
temp);
temp = INREG32(&g_pIPU->DI_DISP_SIG_POL) & 0xE0FFFFFF;
//... DI_DISP_SIG_POL
OUTREG32(&g_pIPU->DI_DISP_SIG_POL,
//..1: inverse data polarity
CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_DATA_POL, m_SignalPol.DATA_POL)|
//..display interface clock polarity
CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_CLK_POL, m_SignalPol.CLK_POL)|
//..1: active high horizontal signal polarity
CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_HSYNC_POL, m_SignalPol.HSYNC_POL)|
//..1: active high vertical signal polarity
CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_VSYNC_POL, m_SignalPol.VSYNC_POL)|
// output enable polarity
CSP_BITFVAL( IPU_DI_DISP_SIG_POL_D3_DRDY_SHARP_POL, m_SignalPol.ENABLE_POL) |
// old value
temp);
// DI_CLK = HSP_CLK * HSP_CLOCK_PER
// ==> HSP_CLOCK_PER = 1
// these are 7 bit fields iiiffff
// where i = integer part and f = fractional part of the value
OUTREG32(&g_pIPU->DI_HSP_CLK_PER,
CSP_BITFVAL( IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_1, 1 << 4) |
CSP_BITFVAL( IPU_DI_HSP_CLK_PER_HSP_CLK_PERIOD_2, 1 << 4));
// DI_DISP3_TIME_CONF = DI_CLK / DISP3_IF_CLK_PER_WR = 133 MHz / 20 = 6.65MHz
m_PixelClock = (currentPanel -> WIDTH + currentPanel -> HSTARTWIDTH + currentPanel -> HSYNCWIDTH + currentPanel -> HENDWIDTH) * \
(currentPanel -> HEIGHT + currentPanel -> VSTARTWIDTH + currentPanel -> VSYNCWIDTH + currentPanel -> VENDWIDTH) * 60;
DDKClockGetFreq(DDK_CLOCK_SIGNAL_IPU, &g_IPUClk);
m_PixelDivider = (g_IPUClk << 4) / m_PixelClock; // g_IPUClk is 0x3F6B5A0
if (m_PixelDivider < 0x40) // Divider less than 4
{
DEBUGMSG(SDC_ERROR,
(TEXT("InitPanel() - Pixel clock divider less than 1\r\n")));
m_PixelDivider = 0x40;
}
switch (currentPanel -> TYPE)
{
case IPU_PANEL_SHARP_TFT:
OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,
//..write strobe end
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, (m_PixelDivider / 8) - 1) |
//.. period
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, m_PixelDivider));
break;
case IPU_PANEL_NEC_TFT:
OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,
//.. period
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, 5 << 4)|
//..write strobe start
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_UP_WR, 0)|
//..write strobe end
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, 3 << 2));
break;
case IPU_TV_NTSC:
case IPU_TV_PAL:
OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,
//.. period
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, 5 << 4)|
//..write strobe start
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_UP_WR, 0)|
//..write strobe end
CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, (2 << 2|2)));
break;
}
//... DI_DISP_ACC_CC
INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
// display clock cycles number (data access)
IPU_DI_DISP_ACC_CC_DISP3_IF_CLK_CNT_D, 0);
//... DI_DISP3_B0_MAP
OUTREG32(&g_pIPU->DI_DISP3_B0_MAP,
// set0; data offset
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS0, 0x5)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS1, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS2, 0)|
// set0; data maping
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M0, 3)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M1, 3)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M2, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M3, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M4, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M5, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M6, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M7, 0));
//... DI_DISP3_B1_MAP
OUTREG32(&g_pIPU->DI_DISP3_B1_MAP,
// set1; data offset
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS0, 0xb)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS1, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS2, 0)|
// set1; data maping
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M0, 3)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M1, 3)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M2, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M3, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M4, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M5, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M6, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M7, 0));
//... DI_DISP3_B2_MAP
OUTREG32(&g_pIPU->DI_DISP3_B2_MAP,
// set2; data offset
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS0, 0x11)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS1, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS2, 0)|
// set2; data maping
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M0, 3)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M1, 3)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M2, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M3, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M4, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M5, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M6, 0)|
CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M7, 0));
//----- SDC Configuration
INSREG32BF(&g_pIPU->SDC_COM_CONF,
IPU_SDC_COM_CONF_GWSEL, IPU_SDC_COM_CONF_GWSEL_BG);
INSREG32BF(&g_pIPU->SDC_COM_CONF,
IPU_SDC_COM_CONF_SDC_GLB_LOC_A, 1);
#ifdef VPMX31
OUTREG32(&g_pIPU->SDC_BG_POS,
CSP_BITFVAL( IPU_SDC_BG_POS_BGXP, 0x0)|
CSP_BITFVAL( IPU_SDC_BG_POS_BGYP, 0x0));
OUTREG32(&g_pIPU->SDC_FG_POS,
CSP_BITFVAL( IPU_SDC_FG_POS_FGXP, 0x0)|
CSP_BITFVAL( IPU_SDC_FG_POS_FGYP, 0x0));
#else
g_iXValMax = currentPanel -> HSTARTWIDTH + currentPanel -> WIDTH;
OUTREG32(&g_pIPU->SDC_BG_POS,
CSP_BITFVAL( IPU_SDC_BG_POS_BGXP, currentPanel -> HSTARTWIDTH )|
CSP_BITFVAL( IPU_SDC_BG_POS_BGYP, currentPanel -> VSTARTWIDTH ));
OUTREG32(&g_pIPU->SDC_FG_POS,
CSP_BITFVAL( IPU_SDC_FG_POS_FGXP, (currentPanel -> HSTARTWIDTH + 1) )|
CSP_BITFVAL( IPU_SDC_FG_POS_FGYP, currentPanel -> VSTARTWIDTH ));
#endif
//----- IDMAC Configuration
// Set no double-buffer, use buf0
INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF);
INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF);
// Set buffer 0 as current buffer (non double buffered)
INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF);
INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF);
// Set high priority for DMA SDC Channel 0
INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,
IPU_DMA_CHA_DMASDC_0, 1);
// Set high priority for DMA SDC Channel 1
INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,
IPU_DMA_CHA_DMASDC_1, 1);
// Set max for consecutive bursts for each channel
INSREG32BF(&g_pIPU->IDMAC_CONF,
IPU_IDMAC_CONF_SRCNT, 7);
// Select source of SDC channel as ARM
OUTREG32(&g_pIPU->IPU_FS_DISP_FLOW,
CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC0_SRC_SEL, FLOW_ARM)|
CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC1_SRC_SEL, FLOW_ARM));
// Turn contrast fully on
OUTREG32(&g_pIPU->SDC_CUR_BLINK_PWM_CTRL,
CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_SCR, 1)|
CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_CC_EN, 1)|
CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_PWM, 0x8F));
_init_dma(currentPanel -> WIDTH, currentPanel -> HEIGHT, bpp, (currentPanel -> WIDTH * bpp / 8), FALSE, SDC_DMA_CHANNEL);
g_pCurrentPanel = currentPanel;
ret = TRUE;
return ret;
}
//------------------------------------------------------------------------------
//
// Function: EnableSDC
//
// This function enables SDC for normal opertion
//
// Parameters:
// none
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