📄 sdc.c
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//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2007, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File: sdc.c
//
// Init IPU for SDC operations
//
//------------------------------------------------------------------------------
#include <windows.h>
#include <Winbase.h>
#include <ceddk.h>
#include "bsp.h"
#include "ipu.h"
#include "sdc.h"
//------------------------------------------------------------------------------
// External Functions
//------------------------------------------------------------------------------
// External Variables
//------------------------------------------------------------------------------
// Defines
#define SDC_DMA_CHANNEL IPU_DMA_CHA_DMASDC_0_LSH // background
#define VF_DMA_CHANNEL IPU_DMA_CHA_DMASDC_1_LSH // foreground
#define GRAPHICS_DMA_CHANNEL IPU_DMA_CHA_DMASDC_1_LSH // foreground
#define FLOW_ARM 0
#define FLOW_ROT_VF 1
#define FLOW_ROT_PP 2
#define FLOW_VF 3
#define FLOW_PP 4
#define FLOW_SNOOP 5
#define FLOW_AUTO_REF 6
#define FLOW_AUTO_REF_SNOOP 7
#define SDC_ERROR DEBUGZONE(0)
#define DELAYTIMEOUT 20000
#define TVOUT_FS453 1
//------------------------------------------------------------------------------
// Types
//------------------------------------------------------------------------------
// Global Variables
PCSP_IPU_REGS g_pIPU;
static HANDLE g_hIPUBase = NULL;
UINT32 g_IPUClk;
PANEL_INFO g_PanelArray[numPanel] =
{
// Sharp Definitions
{
"Sharp QVGA Panel", // Name
IPU_PANEL_SHARP_TFT, // type
IPU_PIX_FMT_RGB565, // Pixel Format
DISPLAY_MODE_DEVICE, // Mode ID
240, // width
320, // height
60, // frequency
1, // Vertical Sync width
8, // Vertical Start Width
80, // Vertical End Width
1, // Horizontal Sync Width
3, // Horizontal Start Width
10, // Horizontal End Width
0, // Write Cycle Period
0, // Write Up Position
0, // Write Down Position
0, // Read Cycle Period
0, // Read Up Position
0, // Read Down Position
0, // Pixel Clock Cyle Frequency
0, // Pixel Data Offset Position
{ // ADC Display Interface signal polarities
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
},
{ // Display Interface signal polarities
FALSE, // Data mask enable
TRUE, // Clock Idle enable
FALSE, // Clock Select Enable
FALSE, // Vertical Sync Polarity
FALSE, // Output enable polarity(straight polarity for sharp signals)
TRUE, // Data Pol Inverse polarity.
TRUE, // Clock Pol Inverse polarity.
TRUE, // HSync Pol
}
},
//NEC VGA Panel definitions
{
"NEC VGA Panel", // Name
IPU_PANEL_NEC_TFT, // type
IPU_PIX_FMT_RGB666, // Pixel Format
DISPLAY_MODE_DEVICE, // Mode ID
640, // width
480, // height
60, // frequency
1, // Vertical Sync width
0x22, // Vertical Start Width 34
40, // Vertical End Width
1, // Horizontal Sync Width
0x90, // Horizontal Start Width 144
0, // Horizontal End Width
0, // Write Cycle Period
0, // Write Up Position
0, // Write Down Position
0, // Read Cycle Period
0, // Read Up Position
0, // Read Down Position
0, // Pixel Clock Cyle Frequency
0, // Pixel Data Offset Position
{ // ADC Display Interface signal polarities
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
},
{ //Display Interface signal polarities
FALSE, // Data mask enable
FALSE, // Clock Idle enable
FALSE, // Clock Select Enable
FALSE, // Vertical Sync Polarity
TRUE, // Output enable polarity(inverse polarity for VGA signals)
FALSE, // Data Pol Straight polarity.
FALSE, // Clock Pol Straight polarity.
FALSE, // HSync Pol
}
},
// NTSC TV mode definitions
{
"NTSC", // Name
IPU_TV_NTSC, // type
IPU_PIX_FMT_RGB565, // Pixel Format
DISPLAY_MODE_NTSC, // Mode ID
640, // width
480, // height
60, // frequency
6, // Vertical Sync width
20, // Vertical Start Width 34
20, // Vertical End Width
64, // Horizontal Sync Width
104, // Horizontal Start Width 144
103, // Horizontal End Width
0, // Write Cycle Period
0, // Write Up Position
0, // Write Down Position
0, // Read Cycle Period
0, // Read Up Position
0, // Read Down Position
0, // Pixel Clock Cyle Frequency
0, // Pixel Data Offset Position
{ // ADC Display Interface signal polarities
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
},
{ //Display Interface signal polarities
FALSE, // Data mask enable
FALSE, // Clock Idle enable
FALSE, // Clock Select Enable
FALSE, // Vertical Sync Polarity
FALSE, // Output enable polarity(inverse polarity for VGA signals)
FALSE, // Data Pol Inverse polarity.
FALSE, // Clock Pol Inverse polarity.
FALSE, // HSync Pol
}
},
// PAL TV mode definitions
{
"PAL", // Name
IPU_TV_PAL, // type
IPU_PIX_FMT_RGB565, // Pixel Format
DISPLAY_MODE_PAL, // Mode ID
640, // width
480, // height
60, // frequency
6, // Vertical Sync width
24, // Vertical Start Width 34
24, // Vertical End Width
64, // Horizontal Sync Width
180, // Horizontal Start Width 144
180, // Horizontal End Width
0, // Write Cycle Period
0, // Write Up Position
0, // Write Down Position
0, // Read Cycle Period
0, // Read Up Position
0, // Read Down Position
0, // Pixel Clock Cyle Frequency
0, // Pixel Data Offset Position
{ // ADC Display Interface signal polarities
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
},
{ //Display Interface signal polarities
FALSE, // Data mask enable
FALSE, // Clock Idle enable
FALSE, // Clock Select Enable
FALSE, // Vertical Sync Polarity
FALSE, // Output enable polarity(inverse polarity for VGA signals)
FALSE, // Data Pol Inverse polarity.
FALSE, // Clock Pol Inverse polarity.
FALSE, // HSync Pol
}
},
// New Panel definitions go here
// Put other Panel info here in future expasion
};
//------------------------------------------------------------------------------
// Local Variables
static HANDLE ipu_mutex;
static BOOL need_map = TRUE;
static HANDLE g_hSDCBGIntrEvent = NULL;
static HANDLE g_hSDCFGIntrEvent = NULL;
static HANDLE g_hSDCIntrThread = NULL;
static const UINT32 m_RefreshRate = 60;
static UINT8 g_iSDCFGNextBuffer = 0;
static PANEL_INFO *g_pCurrentPanel;
static UINT32 g_SDCFGBuf_Saved = 0;
static int g_iXValMax = 0;
static int g_iCurrentFGXP = 0;
//------------------------------------------------------------------------------
// Local Functions
static void _init_dma(int width, int height, int bpp, int stride, BOOL vFlip, const channel);
static void SetSrcBuffer(int channel, PHYSICAL_ADDRESS *pAddr, DISP_BUF_TYPE bufNum);
//------------------------------------------------------------------------------
//
// Function: InitializeSDC
//
// This function initializes SDC related bits in IPU common registers, the
// IPU SDC registers and IDMAC registers for SDC operation.
//
// Parameters:
// width
// [in] width of the display
// height
// [in] height of the display
// bpp
// [in] bits per pixel of the display
//
// Returns:
// TRUE if successful.
//------------------------------------------------------------------------------
UINT32 InitializeSDC(PANEL_INFO *currentPanel, int bpp)
{
UINT32 ret = FALSE, temp = 0, m_PixelClock = 0, m_PixelDivider;
PHYSICAL_ADDRESS phyAddr;
SDC_IPU_DI_SIGNAL_CFG m_SignalPol; // variable to contain Polling information
m_SignalPol = currentPanel -> SDC_SIG_POL;
if (need_map == TRUE)
{
phyAddr.QuadPart = CSP_BASE_REG_PA_IPU;
// Map peripheral physical address to virtual address
g_pIPU = (PCSP_IPU_REGS)MmMapIoSpace(phyAddr, sizeof(CSP_IPU_REGS), FALSE);
// Check if virtual mapping failed
if (g_pIPU == NULL)
{
DEBUGMSG(SDC_ERROR,
(TEXT("%s(): MmMapIoSpace failed!\r\n"), __WFUNCTION__));
return ret;
}
// Turn on clock for IPU
DDKClockSetGatingMode(DDK_CLOCK_GATE_INDEX_IPU, DDK_CLOCK_GATE_MODE_ENABLED_ALL);
need_map = FALSE;
}
// Create event for IPU interrupt for SDC BG EOF
g_hSDCBGIntrEvent = CreateEvent(NULL, FALSE, FALSE, IPU_SDC_BG_INTR_EVENT);
if (g_hSDCBGIntrEvent == NULL)
{
DEBUGMSG(SDC_ERROR,
(TEXT("%s: CreateEvent for IPU Interrupt failed\r\n"), __WFUNCTION__));
return ret;
}
// Create event for IPU interrupt for SDC FG EOF
g_hSDCFGIntrEvent = CreateEvent(NULL, FALSE, FALSE, IPU_SDC_FG_INTR_EVENT);
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