di_init.c

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
//  File:  di_init.c
//
//  Init DI for ADC operations
//
//------------------------------------------------------------------------------
#include <windows.h>
#include <ceddk.h>
#include "bsp.h"
#include "di_init.h"

//------------------------------------------------------------------------------
// External Functions


//------------------------------------------------------------------------------
// External Variables
extern PCSP_IPU_REGS g_pIPU;


//------------------------------------------------------------------------------
// Defines
#define     COMMAND_INFO        0
#define     DATA_INFO           1


//------------------------------------------------------------------------------
// Types


//------------------------------------------------------------------------------
// Global Variables


//------------------------------------------------------------------------------
// Local Variables


//------------------------------------------------------------------------------
// Local Functions
static void set_data_mapping(unsigned int display, unsigned int map0,
                             unsigned int map1, unsigned int map2);
static void set_cmd_mapping(unsigned int display, unsigned int map0,
                            unsigned int map1, unsigned int map2);
static void set_cycles(unsigned int display, unsigned int type,
                       unsigned int cycles);


//Setup the mapping for sending commands to Smart Display
void DICommandMapping(unsigned int display)
{
    unsigned int map0 = 0x00070000;
    unsigned int map1 = 0x0000FFFF; //Masked
    unsigned int map2 = 0x0000FFFF; //Masked
    unsigned int cycles = IPU_DI_DISP_ACC_CC_CLOCK_1_CYCLE;

    set_cmd_mapping(display, map0, map1, map2);
    set_cycles(display, COMMAND_INFO, cycles);
}


//Setup DI for RGB565
void DIRGB565(unsigned int display)
{
    // Maybe this is a bug in Virtio.  I have to switch Red and Blue.
    // Verify this with real hardware!!!
    unsigned int map0 = 0x0004003F;
    unsigned int map1 = 0x000A000F;
    unsigned int map2 = 0x000F003F;
    unsigned int cycles = IPU_DI_DISP_ACC_CC_CLOCK_1_CYCLE;

    set_data_mapping(display, map0, map1, map2);
    set_cycles(display, DATA_INFO, cycles);
}


//Setup DI for converting from RGB888 to RGB666
void DIRGB888To666(unsigned int display)
{
    unsigned int map0 = 0x1400AAAF;
    unsigned int map1 = 0x00A0555F;
    unsigned int map2 = 0x0005000F;
    unsigned int cycles = IPU_DI_DISP_ACC_CC_CLOCK_3_CYCLE;

    set_data_mapping(display, map0, map1, map2);
    set_cycles(display, DATA_INFO, cycles);
}


//Setup a new data mapping
void set_data_mapping(unsigned int display, unsigned int map0,
                      unsigned int map1, unsigned int map2)
{
    switch (display)
    {
    case IPU_ADC_DISPLAY_0:
        OUTREG32(&g_pIPU->DI_DISP0_DB0_MAP, map0);
        OUTREG32(&g_pIPU->DI_DISP0_DB1_MAP, map1);
        OUTREG32(&g_pIPU->DI_DISP0_DB2_MAP, map2);
        break;

    case IPU_ADC_DISPLAY_1:
        OUTREG32(&g_pIPU->DI_DISP1_DB0_MAP, map0);
        OUTREG32(&g_pIPU->DI_DISP1_DB1_MAP, map1);
        OUTREG32(&g_pIPU->DI_DISP1_DB2_MAP, map2);
        break;

    case IPU_ADC_DISPLAY_2:
        OUTREG32(&g_pIPU->DI_DISP2_DB0_MAP, map0);
        OUTREG32(&g_pIPU->DI_DISP2_DB1_MAP, map1);
        OUTREG32(&g_pIPU->DI_DISP2_DB2_MAP, map2);
        break;

    case IPU_ADC_DISPLAY_3:
        OUTREG32(&g_pIPU->DI_DISP3_B0_MAP, map0);
        OUTREG32(&g_pIPU->DI_DISP3_B1_MAP, map1);
        OUTREG32(&g_pIPU->DI_DISP3_B2_MAP, map2);
        break;

    default:
        break;
    }
}

//Setup a new command mapping
void set_cmd_mapping(unsigned int display, unsigned int map0,
                     unsigned int map1, unsigned int map2)
{
    switch(display)
    {
    case IPU_ADC_DISPLAY_0:
        OUTREG32(&g_pIPU->DI_DISP0_CB0_MAP, map0);
        OUTREG32(&g_pIPU->DI_DISP0_CB1_MAP, map1);
        OUTREG32(&g_pIPU->DI_DISP0_CB2_MAP, map2);
        break;

    case IPU_ADC_DISPLAY_1:
        OUTREG32(&g_pIPU->DI_DISP1_CB0_MAP, map0);
        OUTREG32(&g_pIPU->DI_DISP1_CB1_MAP, map1);
        OUTREG32(&g_pIPU->DI_DISP1_CB2_MAP, map2);
        break;

    case IPU_ADC_DISPLAY_2:
        OUTREG32(&g_pIPU->DI_DISP2_CB0_MAP, map0);
        OUTREG32(&g_pIPU->DI_DISP2_CB1_MAP, map1);
        OUTREG32(&g_pIPU->DI_DISP2_CB2_MAP, map2);
        break;

    default:
        break;
    }
}

//Set the number of cycles to use
void set_cycles(unsigned int display, unsigned int type, unsigned int cycles)
{

    switch (display)
    {
    case IPU_ADC_DISPLAY_0:
    default:
        if (COMMAND_INFO != type)
        {
            INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                       IPU_DI_DISP_ACC_CC_DISP0_IF_CLK_CNT_D,
                       cycles);
        }
        else
        {
            INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                       IPU_DI_DISP_ACC_CC_DISP0_IF_CLK_CNT_C,
                       cycles);
        }
        break;

    case IPU_ADC_DISPLAY_1:
        if (COMMAND_INFO != type)
        {
            INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                       IPU_DI_DISP_ACC_CC_DISP1_IF_CLK_CNT_D,
                       cycles);
        }
        else
        {
            INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                       IPU_DI_DISP_ACC_CC_DISP1_IF_CLK_CNT_C,
                       cycles);
        }
        break;

    case IPU_ADC_DISPLAY_2:
        if (COMMAND_INFO != type)
        {
            INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                       IPU_DI_DISP_ACC_CC_DISP2_IF_CLK_CNT_D,
                       cycles);
        }
        else
        {
            INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                       IPU_DI_DISP_ACC_CC_DISP2_IF_CLK_CNT_C,
                       cycles);
        }
        break;

    case IPU_ADC_DISPLAY_3:
        //No commands for display 3
        INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                   IPU_DI_DISP_ACC_CC_DISP3_IF_CLK_CNT_D,
                   cycles);
        break;
    }

}