bspfir.c

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004, Motorola Inc. All Rights Reserved
//
//-----------------------------------------------------------------------------
/*---------------------------------------------------------------------------
* Copyright (C) 2004 - 2006, Freescale Semiconductor, Inc. All Rights Reserved.
* THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
* AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT 
*--------------------------------------------------------------------------*/
//------------------------------------------------------------------------------
//
//  File:  bspFir.c
//
//  Provides BSP-specific configuration routines for the UART peripheral.
//
//------------------------------------------------------------------------------
#include <windows.h>
#include "bsp.h"
#include "bspSerial.c"
#include "bspIrda.c"

//-----------------------------------------------------------------------------
// External Functions

//-----------------------------------------------------------------------------
// External Variables

//-----------------------------------------------------------------------------
// Defines

//-----------------------------------------------------------------------------
// Types

//-----------------------------------------------------------------------------
// Global Variables

//-----------------------------------------------------------------------------
// Local Variables

//------------------------------------------------------------------------------
// Local Functions

//-----------------------------------------------------------------------------
//
// Function: BSPFirEnableClock
//
// This function is a wrapper for Fir to enable/disable its clock using a valid
// CRM handle.
//
// Parameters:
//      bEnable
//          [in] TRUE if Fir Clock is to be enabled. FALSE if Fir Clock is
//                to be disabled.
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPFirEnableClock(BOOL bEnable)
{
    BOOL result = FALSE;


    if (bEnable)
        result = DDKClockSetGatingMode(DDK_CLOCK_GATE_INDEX_FIRI, 
            DDK_CLOCK_GATE_MODE_ENABLED_ALL);
    else
        result = DDKClockSetGatingMode(DDK_CLOCK_GATE_INDEX_FIRI, 
            DDK_CLOCK_GATE_MODE_DISABLED);

    return result;
}
//-----------------------------------------------------------------------------
//
// Function: BSPFirSetIOMUX
//
// This function is a wrapper for Fir to enable/disable its Hardware Mode
//
// Parameters:
//      No parameter
//
// Returns:
//      TRUE if successfully performed the required action.
//
// Remarks:
//		This function will set set the bits to the Hardware mode.
//
//-----------------------------------------------------------------------------
BOOL BSPFirSetIOMUX(void)
{
	return DDKIomuxSetGprBit(DDK_IOMUX_GPR_FIRI_UART2, 1);
}
//-----------------------------------------------------------------------------
//
// Function: BSPSirSetIOMUX
//
// This function Set the UART2 in FIR or SIR mode
//
// Parameters:
//      No parameter
//
// Returns:
//      TRUE if successfully performed the required action.
//
// Remarks:
//		This function will set the signals back to normal mode amd 
//		configure the pins accordingly to SIR mode.
//
//-----------------------------------------------------------------------------
BOOL BSPFirSetSIRIOMUX(void)
{
	BOOL bRet = FALSE;

	// set the pin back to the original state
	bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_FIRI_UART2, 0);
	// Configure the pins accordingly
	bRet = DDKIomuxSetPinMux(DDK_IOMUX_PIN_TXD2, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
	bRet = DDKIomuxSetPinMux(DDK_IOMUX_PIN_RXD2, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);

	return bRet;
}
//-----------------------------------------------------------------------------
//
// Function: BSPFirSetClock
//
// This function is a wrapper for Fir to set its clock to
//		corresponging PLL and value
//
// Parameters:
//		None
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPFirSetClock(void)
{
	// ideal clock for 4 Mbps should be a multiple of 8 MHz
	// And the multiplication factor is 6
	// USB PLL Frequency = 240MHz
	// In the FIRI programming examples, configure CCM, 
	// frequency ipg_clk_firi_baud to 48MHz.
	// So internal divider is 240 / 48 = 5 
	// So post divider is 4.
    return DDKClockConfigBaud(DDK_CLOCK_SIGNAL_FIRI,DDK_CLOCK_BAUD_SOURCE_USBPLL, 0,4);
}
//-----------------------------------------------------------------------------
//
// Function: BSPFirGetChannelPriority
//
// This function return the SDMA channel priority
//
// Parameters:
//		None
//
// Returns:
//      Returns the channel priority.
//
//-----------------------------------------------------------------------------
UINT8 BSPFirGetChannelPriority(void)
{
    return BSP_SDMA_CHNPRI_FIRI;
}